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Received: from DS0SPRMB0124.namprd12.prod.outlook.com (2603:10b6:8:1fa::20) by CH4PR12MB590718.namprd12.prod.outlook.com (2603:10b6:610:50f::5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.10; Fri, 6 Nov 2026 11:10:39 +0000 Received: from DS0SPRMB0124.namprd12.prod.outlook.com ([fe80::24e7:97e0:923e:68d6]) by DS0SPRMB0124.namprd12.prod.outlook.com ([fe80::24e7:97e0:923e:68d6%6]) with mapi id 15.21.0592.007; Fri, 6 Nov 2026 11:10:39 +0000 Message-ID: <9b3280d4-1fd9-4129-9ddf-2f58d404fd33@amd.com> Date: Fri, 6 Nov 2026 16:40:31 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 3/4] dmaengine: zynqmp_dma: Add new compatible string for Versal Net To: Golla Nagendra , Vinod Koul , Frank Li , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michal Simek , Michael Tretter , Harini Katakam , Shyam Pandey , Abin Joseph Cc: Krzysztof Kozlowski , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, git@amd.com References: <20261106-adma_per_channel_reset_v5-v5-0-f9990669362f@amd.com> <20261106-adma_per_channel_reset_v5-v5-3-f9990669362f@amd.com> Content-Language: en-US From: "Pandey, Radhey Shyam" In-Reply-To: <20261106-adma_per_channel_reset_v5-v5-3-f9990669362f@amd.com> Content-Type: text/plain; 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Add amd,versal-net-dma-1.0 to the of_device_id match table > with SoC-specific match data via versal_net_dma_config. > > Introduce a has_reset field in zynqmp_dma_config to indicate whether > the compatible requires a per-channel reset during probe. > > Signed-off-by: Golla Nagendra Reviewed-by: Radhey Shyam Pandey Thanks! > --- > drivers/dma/xilinx/zynqmp_dma.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/dma/xilinx/zynqmp_dma.c b/drivers/dma/xilinx/zynqmp_dma.c > index 3b7dfa53f972..cb0eb13f9b05 100644 > --- a/drivers/dma/xilinx/zynqmp_dma.c > +++ b/drivers/dma/xilinx/zynqmp_dma.c > @@ -257,13 +257,20 @@ struct zynqmp_dma_device { > }; > > struct zynqmp_dma_config { > + bool has_reset; > u32 offset; > }; > > static const struct zynqmp_dma_config versal2_dma_config = { > + .has_reset = true, > .offset = IRQ_REG_OFFSET, > }; > > +/* offset = 0: Versal Net uses base IRQ register address */ > +static const struct zynqmp_dma_config versal_net_dma_config = { > + .has_reset = true, > +}; > + > static inline void zynqmp_dma_writeq(struct zynqmp_dma_chan *chan, u32 reg, > u64 value) > { > @@ -1193,6 +1200,7 @@ static void zynqmp_dma_remove(struct platform_device *pdev) > > static const struct of_device_id zynqmp_dma_of_match[] = { > { .compatible = "amd,versal2-dma-1.0", .data = &versal2_dma_config }, > + { .compatible = "amd,versal-net-dma-1.0", .data = &versal_net_dma_config }, > { .compatible = "xlnx,zynqmp-dma-1.0", }, > {} > }; >