From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5675F3A89DD; Tue, 20 Jan 2026 07:43:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.19 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768895022; cv=none; b=GY39FF6QXCl5z4ghcwnRwPN8tZiqFv5vUN3bI3INDlA6/N7RpScZS3U5N/HP7QiZoQpM88vEAqXDBeGM1T0AoxgkqXj2sEEcVJhua3VG5EjjYiksPzmcbVLIEFe+/DuoWAewJTQ67/lOu+nWhGHhmG7k1ZN2Vf5xMYwyecHU91E= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768895022; c=relaxed/simple; bh=YRQEfMnWIT/sjwi96Q33wCRw82Od4zkV7AS9HFQf8wY=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=ONDajBHJuZWZZE1eEGwJfNp4bOg7cGSraQvUmI63vzHicf6HSZl8nTra7mtUjCbq2Shsv8dGBlosB9+s470CBNWd5M0bpuRYjJh94NYUM3HK492W2iAYICE/PdZtKA3jA3+YuWJPUDQRMblNl1ycEw0l5q6PcaPjLbbSfF3OJs8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=pass smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=GAi9AEnm; arc=none smtp.client-ip=192.198.163.19 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="GAi9AEnm" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1768895019; x=1800431019; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=YRQEfMnWIT/sjwi96Q33wCRw82Od4zkV7AS9HFQf8wY=; b=GAi9AEnm7UXATAIn0W1wTAYX+WtFWadhTynIK/nglv9+B4ZAV8metwDe DzKVMrqmD9vFZbiaRFME7SUEGNv3BkUJwMQcAY2mv7s0beu4D/XwOIYIi Pd3gwdcWhapAqv+Xwk6XdW+e0ZPx3102w5PlMJZ0gLXrGkejMun2JAMRm P+SXJ+tbApzvN1Mu7aBCLRfD2Mafpm0P7C1+ku6jlcibA29PIxI4KXyC7 v79/JmHecneXMIN2iuteeIVMkfnEoO5hkE/27wjJjPjR4ZFwRWPjtNeBm tXRc4uB9wnZTuIL3q0DeiVBFhODB3bUn4e2Wf7CBrFFePS8Zm7D6t/0hq A==; X-CSE-ConnectionGUID: TWF/lszAR4Odht3Nyu4jZQ== X-CSE-MsgGUID: 7iT0tWqbR5GxWDPcdnAgSw== X-IronPort-AV: E=McAfee;i="6800,10657,11676"; a="69107913" X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="69107913" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 23:43:38 -0800 X-CSE-ConnectionGUID: 2QpPsRW9SmuJtXBe+OEfgw== X-CSE-MsgGUID: cikL+/rNSuG5JurqrehkQg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,240,1763452800"; d="scan'208";a="210191429" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.240.14]) ([10.124.240.14]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Jan 2026 23:43:32 -0800 Message-ID: <9b429aa8-d269-4af8-9236-350cb9543f2a@linux.intel.com> Date: Tue, 20 Jan 2026 15:43:29 +0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [Patch v5 17/19] perf headers: Sync with the kernel headers To: Ian Rogers Cc: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Gleixner , Dave Hansen , Adrian Hunter , Jiri Olsa , Alexander Shishkin , Andi Kleen , Eranian Stephane , Mark Rutland , broonie@kernel.org, Ravi Bangoria , linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, Zide Chen , Falcon Thomas , Dapeng Mi , Xudong Hao , Kan Liang References: <20251203065500.2597594-1-dapeng1.mi@linux.intel.com> <20251203065500.2597594-18-dapeng1.mi@linux.intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 1/20/2026 3:16 PM, Ian Rogers wrote: > On Tue, Dec 2, 2025 at 10:59 PM Dapeng Mi wrote: >> From: Kan Liang >> >> Update include/uapi/linux/perf_event.h and >> arch/x86/include/uapi/asm/perf_regs.h to support extended regs. >> >> Signed-off-by: Kan Liang >> Co-developed-by: Dapeng Mi >> Signed-off-by: Dapeng Mi >> --- >> tools/arch/x86/include/uapi/asm/perf_regs.h | 62 +++++++++++++++++++++ >> tools/include/uapi/linux/perf_event.h | 45 +++++++++++++-- >> 2 files changed, 103 insertions(+), 4 deletions(-) >> >> diff --git a/tools/arch/x86/include/uapi/asm/perf_regs.h b/tools/arch/x86/include/uapi/asm/perf_regs.h >> index 7c9d2bb3833b..f3561ed10041 100644 >> --- a/tools/arch/x86/include/uapi/asm/perf_regs.h >> +++ b/tools/arch/x86/include/uapi/asm/perf_regs.h >> @@ -27,9 +27,34 @@ enum perf_event_x86_regs { >> PERF_REG_X86_R13, >> PERF_REG_X86_R14, >> PERF_REG_X86_R15, >> + /* >> + * The EGPRs/SSP and XMM have overlaps. Only one can be used >> + * at a time. For the ABI type PERF_SAMPLE_REGS_ABI_SIMD, >> + * utilize EGPRs/SSP. For the other ABI type, XMM is used. >> + * >> + * Extended GPRs (EGPRs) >> + */ >> + PERF_REG_X86_R16, >> + PERF_REG_X86_R17, >> + PERF_REG_X86_R18, >> + PERF_REG_X86_R19, >> + PERF_REG_X86_R20, >> + PERF_REG_X86_R21, >> + PERF_REG_X86_R22, >> + PERF_REG_X86_R23, >> + PERF_REG_X86_R24, >> + PERF_REG_X86_R25, >> + PERF_REG_X86_R26, >> + PERF_REG_X86_R27, >> + PERF_REG_X86_R28, >> + PERF_REG_X86_R29, >> + PERF_REG_X86_R30, >> + PERF_REG_X86_R31, >> + PERF_REG_X86_SSP, >> /* These are the limits for the GPRs. */ >> PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1, >> PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1, >> + PERF_REG_MISC_MAX = PERF_REG_X86_SSP + 1, >> >> /* These all need two bits set because they are 128bit */ >> PERF_REG_X86_XMM0 = 32, >> @@ -54,5 +79,42 @@ enum perf_event_x86_regs { >> }; >> >> #define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1)) >> +#define PERF_X86_EGPRS_MASK GENMASK_ULL(PERF_REG_X86_R31, PERF_REG_X86_R16) >> + >> +enum { >> + PERF_REG_X86_XMM, >> + PERF_REG_X86_YMM, >> + PERF_REG_X86_ZMM, >> + PERF_REG_X86_MAX_SIMD_REGS, >> + >> + PERF_REG_X86_OPMASK = 0, >> + PERF_REG_X86_MAX_PRED_REGS = 1, >> +}; >> + >> +enum { >> + PERF_X86_SIMD_XMM_REGS = 16, >> + PERF_X86_SIMD_YMM_REGS = 16, >> + PERF_X86_SIMD_ZMMH_REGS = 16, >> + PERF_X86_SIMD_ZMM_REGS = 32, >> + PERF_X86_SIMD_VEC_REGS_MAX = PERF_X86_SIMD_ZMM_REGS, >> + >> + PERF_X86_SIMD_OPMASK_REGS = 8, >> + PERF_X86_SIMD_PRED_REGS_MAX = PERF_X86_SIMD_OPMASK_REGS, >> +}; >> + >> +#define PERF_X86_SIMD_PRED_MASK GENMASK(PERF_X86_SIMD_PRED_REGS_MAX - 1, 0) >> +#define PERF_X86_SIMD_VEC_MASK GENMASK_ULL(PERF_X86_SIMD_VEC_REGS_MAX - 1, 0) >> + >> +#define PERF_X86_H16ZMM_BASE PERF_X86_SIMD_ZMMH_REGS >> + >> +enum { >> + PERF_X86_OPMASK_QWORDS = 1, >> + PERF_X86_XMM_QWORDS = 2, >> + PERF_X86_YMMH_QWORDS = 2, >> + PERF_X86_YMM_QWORDS = 4, >> + PERF_X86_ZMMH_QWORDS = 4, >> + PERF_X86_ZMM_QWORDS = 8, >> + PERF_X86_SIMD_QWORDS_MAX = PERF_X86_ZMM_QWORDS, >> +}; >> >> #endif /* _ASM_X86_PERF_REGS_H */ >> diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/linux/perf_event.h >> index d292f96bc06f..f1474da32622 100644 >> --- a/tools/include/uapi/linux/perf_event.h >> +++ b/tools/include/uapi/linux/perf_event.h >> @@ -314,8 +314,9 @@ enum { >> */ >> enum perf_sample_regs_abi { >> PERF_SAMPLE_REGS_ABI_NONE = 0, >> - PERF_SAMPLE_REGS_ABI_32 = 1, >> - PERF_SAMPLE_REGS_ABI_64 = 2, >> + PERF_SAMPLE_REGS_ABI_32 = (1 << 0), >> + PERF_SAMPLE_REGS_ABI_64 = (1 << 1), >> + PERF_SAMPLE_REGS_ABI_SIMD = (1 << 2), >> }; >> >> /* >> @@ -382,6 +383,7 @@ enum perf_event_read_format { >> #define PERF_ATTR_SIZE_VER6 120 /* Add: aux_sample_size */ >> #define PERF_ATTR_SIZE_VER7 128 /* Add: sig_data */ >> #define PERF_ATTR_SIZE_VER8 136 /* Add: config3 */ >> +#define PERF_ATTR_SIZE_VER9 168 /* Add: sample_simd_{pred,vec}_reg_* */ >> >> /* >> * 'struct perf_event_attr' contains various attributes that define >> @@ -545,6 +547,25 @@ struct perf_event_attr { >> __u64 sig_data; >> >> __u64 config3; /* extension of config2 */ >> + >> + >> + /* >> + * Defines set of SIMD registers to dump on samples. >> + * The sample_simd_regs_enabled !=0 implies the >> + * set of SIMD registers is used to config all SIMD registers. >> + * If !sample_simd_regs_enabled, sample_regs_XXX may be used to >> + * config some SIMD registers on X86. >> + */ >> + union { >> + __u16 sample_simd_regs_enabled; >> + __u16 sample_simd_pred_reg_qwords; >> + }; >> + __u32 sample_simd_pred_reg_intr; >> + __u32 sample_simd_pred_reg_user; >> + __u16 sample_simd_vec_reg_qwords; >> + __u64 sample_simd_vec_reg_intr; >> + __u64 sample_simd_vec_reg_user; >> + __u32 __reserved_4; >> }; >> >> /* >> @@ -1018,7 +1039,15 @@ enum perf_event_type { >> * } && PERF_SAMPLE_BRANCH_STACK >> * >> * { u64 abi; # enum perf_sample_regs_abi >> - * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_USER >> + * u64 regs[weight(mask)]; >> + * struct { >> + * u16 nr_vectors; >> + * u16 vector_qwords; >> + * u16 nr_pred; >> + * u16 pred_qwords; >> + * u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords]; >> + * } && (abi & PERF_SAMPLE_REGS_ABI_SIMD) > Why can't these values be taken from the perf_event_attr? The abi is > needed as there could be both 32-bit and 64-bit samples for the same > event - presumably x32 appears as 64-bit. If the ABI has SIMD within > it (implied by the "} && (abi & PERF_SAMPLE_REGS_ABI_SIMD)" below) > then why can't we just use the perf_event_attr values? For example, > data could be "data[weight(sample_simd_vec_reg_user) * > sample_simd_vec_reg_qwords + weight(sample_simd_pred_reg_user) * > sample_simd_pred_reg_qwords]". The main reason is that the sampled SIMD regs could only be a subset of the requested SIMD regs in perf_event_attr, so we need to show the bitmask and qwords length explicitly in the sample record.  > >> + * } && PERF_SAMPLE_REGS_USER >> * >> * { u64 size; >> * char data[size]; >> @@ -1045,7 +1074,15 @@ enum perf_event_type { >> * { u64 data_src; } && PERF_SAMPLE_DATA_SRC >> * { u64 transaction; } && PERF_SAMPLE_TRANSACTION >> * { u64 abi; # enum perf_sample_regs_abi >> - * u64 regs[weight(mask)]; } && PERF_SAMPLE_REGS_INTR >> + * u64 regs[weight(mask)]; >> + * struct { >> + * u16 nr_vectors; >> + * u16 vector_qwords; >> + * u16 nr_pred; >> + * u16 pred_qwords; >> + * u64 data[nr_vectors * vector_qwords + nr_pred * pred_qwords]; >> + * } && (abi & PERF_SAMPLE_REGS_ABI_SIMD) > Same comment. > > Thanks, > Ian > >> + * } && PERF_SAMPLE_REGS_INTR >> * { u64 phys_addr;} && PERF_SAMPLE_PHYS_ADDR >> * { u64 cgroup;} && PERF_SAMPLE_CGROUP >> * { u64 data_page_size;} && PERF_SAMPLE_DATA_PAGE_SIZE >> -- >> 2.34.1 >>