From: Gabriel FERNANDEZ <gabriel.fernandez@foss.st.com>
To: Conor Dooley <conor@kernel.org>, <sboyd@kernel.org>
Cc: Conor Dooley <conor.dooley@microchip.com>,
Daire McNamara <daire.mcnamara@microchip.com>,
<pierre-henry.moussay@microchip.com>,
<valentina.fernandezalanis@microchip.com>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Jassi Brar <jassisinghbrar@gmail.com>, Lee Jones <lee@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
<linux-riscv@lists.infradead.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v4 8/9] clk: divider, gate: create regmap-backed copies of gate and divider clocks
Date: Tue, 2 Sep 2025 16:05:21 +0200 [thread overview]
Message-ID: <9b669562-ee52-47b6-856e-3184b3e89d28@foss.st.com> (raw)
In-Reply-To: <20250901-yearling-reconcile-99d06fe7868e@spud>
On 9/1/25 13:04, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Implement regmap-backed copies of gate and divider clocks by replacing
> the iomem pointer to the clock registers with a regmap and offset
> within.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> v4:
> - increase map_offset to a u32
> - use a single Kconfig option for both divider and gate regmap
> implementations
> ---
> drivers/clk/Kconfig | 4 +
> drivers/clk/Makefile | 2 +
> drivers/clk/clk-divider-regmap.c | 271 +++++++++++++++++++++++++++++++
> drivers/clk/clk-gate-regmap.c | 254 +++++++++++++++++++++++++++++
> include/linux/clk-provider.h | 119 ++++++++++++++
> 5 files changed, 650 insertions(+)
> create mode 100644 drivers/clk/clk-divider-regmap.c
> create mode 100644 drivers/clk/clk-gate-regmap.c
>
Hi Conor,
i tested the clk_gate_remap part with my code, it works fine.
Just a minor remark concerning .round_rate, you can add my
Reviewed-by: Gabriel Fernandez <gabriel.fernandez@foss.st.com>
> +const struct clk_ops clk_divider_regmap_ops = {
> + .recalc_rate = clk_divider_regmap_recalc_rate,
> + .round_rate = clk_divider_regmap_round_rate,
.round_rate could be removed ?
> + .determine_rate = clk_divider_regmap_determine_rate,
> + .set_rate = clk_divider_regmap_set_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_divider_regmap_ops);
> +
> +const struct clk_ops clk_divider_regmap_ro_ops = {
> + .recalc_rate = clk_divider_regmap_recalc_rate,
> + .round_rate = clk_divider_regmap_round_rate,
dito
> + .determine_rate = clk_divider_regmap_determine_rate,
> +};
> +EXPORT_SYMBOL_GPL(clk_divider_regmap_ro_ops);
> +
next prev parent reply other threads:[~2025-09-02 14:08 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-01 11:04 [PATCH v4 0/9] Redo PolarFire SoC's mailbox/clock devicetrees and related code Conor Dooley
2025-09-01 11:04 ` [PATCH v4 1/9] dt-bindings: mfd: syscon document the control-scb syscon on PolarFire SoC Conor Dooley
2025-09-03 13:19 ` (subset) " Lee Jones
2025-09-01 11:04 ` [PATCH v4 2/9] dt-bindings: soc: microchip: document the simple-mfd " Conor Dooley
2025-09-01 11:04 ` [PATCH v4 3/9] soc: microchip: add mfd drivers for two syscon regions " Conor Dooley
2025-09-01 11:04 ` [PATCH v4 4/9] reset: mpfs: add non-auxiliary bus probing Conor Dooley
2025-09-01 11:04 ` [PATCH v4 5/9] dt-bindings: clk: microchip: mpfs: remove first reg region Conor Dooley
2025-09-01 11:04 ` [PATCH v4 6/9] riscv: dts: microchip: fix mailbox description Conor Dooley
2025-09-01 11:04 ` [PATCH v4 7/9] riscv: dts: microchip: convert clock and reset to use syscon Conor Dooley
2025-09-01 11:04 ` [PATCH v4 8/9] clk: divider, gate: create regmap-backed copies of gate and divider clocks Conor Dooley
2025-09-02 14:05 ` Gabriel FERNANDEZ [this message]
2025-09-01 11:04 ` [PATCH v4 9/9] clk: microchip: mpfs: use regmap clock types Conor Dooley
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