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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BY1PEPF0001AE17.mail.protection.outlook.com (10.167.242.107) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.451.8 via Frontend Transport; Fri, 18 Sep 2026 23:01:56 +0000 Received: from [10.236.30.85] (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Fri, 18 Sep 2026 18:01:55 -0500 Message-ID: <9b85be41-db5a-4bdb-95b4-beffb05a5ffc@amd.com> Date: Fri, 18 Sep 2026 18:01:55 -0500 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/8] x86/bugs: Allow spectre_v2=ibrs on x86 vendors other than Intel To: Borislav Petkov CC: , , , , Sean Christopherson , Paolo Bonzini , K Prateek Nayak , Nikunj A Dadhania , Tom Lendacky , Michael Roth , Naveen Rao , David Kaplan , Pawan Gupta , Dave Hansen , Nathan Fontenot References: <20260826223510.3669875-1-kim.phillips@amd.com> <20260826223510.3669875-3-kim.phillips@amd.com> <20260909210101.GBaqHJDWSUnpjqNcyB@fat_crate.local> Content-Language: en-US From: Kim Phillips In-Reply-To: <20260909210101.GBaqHJDWSUnpjqNcyB@fat_crate.local> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: U+cV2OnSMEdljUOGTpLCUanaQX+mBXeUkJOJzOqNnLX9+5ccGcscNh5oc23bUtDKOKkGVIvqU+lut1Mn3qQo4++vTpWLYT25Tz8xrWMj4dz2wBlOqe5gMmBL/Vk38j6DXTt7LdcqK+/94/pJmgBupefDLw6w/JvWJ9PdSZg3GCLg8bYLjJ1Pb/JLWNu1zYPBOhgleOA3tNFGT0l55aXGsVUdUturNiV1yeT8HuKUFj9HAHtB61P8I1PJnszFISuSjFJyaAM5SBom7cBJi0VxqdxF/qe9L9YB2i54n1EDf0A1MbLvMBIjaQmqWxVuogNMiduKOwpuwr/N6JCD1G/E5DDUIL7HBKkE1ti9S2Y2l9kh7gfWyfMhYUom9D1sJ17ElEx0WfDHS9xRtA1ZGtCGWDSU/DYqqjVnEkQA43Po8sHT/j9pGvWg2f89Pikf3+cz X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 18 Sep 2026 23:01:56.6475 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e0c683cc-d1c6-4590-1def-08df15d8d69b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BY1PEPF0001AE17.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6145 On 9/9/26 4:01 PM, Borislav Petkov wrote: > On Wed, Aug 26, 2026 at 05:35:04PM -0500, Kim Phillips wrote: >> Prepare for legacy IBRS toggling on AMD, where the BTB Isolation > Same question as before: why? > > This commit message is explaining what the patch does. It needs to explain > the why. > ok how about this as the new commit text?: SPEC_CTRL.IBRS is architectural and behaves on AMD just like it does on Intel, but the kernel offers spectre_v2=ibrs on Intel only: the option is rejected at parse time on other vendors, and MITIGATION_IBRS_ENTRY cannot even be built into an AMD-only kernel. AMD's SNP BTB Isolation needs the kernel to toggle legacy IBRS in order to optimize the VM exit-to-re-entry path, and right now there is no way to ask for kernel IBRS on an AMD machine at all. It happens for historical reasons only.  Commit 7c693f54c873 ("x86/speculation: Add spectre_v2=ibrs option to support Kernel IBRS") gated the option on Intel because Intel was the only vendor that needed it back then - there, kernel IBRS doubles as a RETBleed mitigation. Nothing in the IBRS_ENTER/IBRS_EXIT mechanism itself is vendor-specific. Fix it by dropping the vendor check from the command line parsing and CPU_SUP_INTEL from MITIGATION_IBRS_ENTRY's depends line. Keep the IBRS-trumps-retbleed logic in retbleed_update_mitigation() Intel-only, though: legacy SPEC_CTRL.IBRS does not cover AMD's Branch Type Confusion RETBleed variant because RET prediction comes from the Return Address Predictor rather than from the indirect branch predictors IBRS restricts.  Letting SPECTRE_V2_IBRS trump retbleed on AMD would silently drop the UNRET/IBPB mitigation that does cover it.  RETBleed selection on AMD never consults spectre_v2=, so spectre_v2=ibrs neither adds nor removes RETBleed coverage there and the retbleed sysfs node keeps reporting the truth on its own. Two more things need handling once the option becomes reachable on AMD: AutoIBRS-capable CPUs would take the EFER.AUTOIBRS path for any IBRS mode, handing spectre_v2=ibrs the always-on AutoIBRS behaviour instead of the toggleable SPEC_CTRL.IBRS the option asks for.  Restrict that path to the eIBRS modes. And EFER.AUTOIBRS survives kexec because head_64.S preserves the incoming EFER bits, so a kernel that ran in AutoIBRS mode leaves the next one in AutoIBRS mode while its sysfs reports "Mitigation: IBRS" or a retpoline mode.  Clear the bit at the top of cpu_select_mitigations() next to the existing SPEC_CTRL kexec cleanup - a cold boot has it clear already, and that spot precedes the init_real_mode() EFER snapshot the AP trampoline uses. Thanks, Kim