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Thu, 02 Oct 2025 02:41:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGrQXdvyBSld64O1fXcWJnNXjuF1iF9neRdC1GOocwtAa/1NbRXNWOkpTU61PS7Mqc8K7jbKA== X-Received: by 2002:a17:90b:1a91:b0:32e:1b1c:f8b8 with SMTP id 98e67ed59e1d1-339a6f58396mr8008587a91.26.1759398069409; Thu, 02 Oct 2025 02:41:09 -0700 (PDT) Received: from [10.204.101.186] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-339a701c061sm4473608a91.22.2025.10.02.02.41.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 02 Oct 2025 02:41:08 -0700 (PDT) Message-ID: <9b8d587d-553f-47aa-7203-a2a573208990@oss.qualcomm.com> Date: Thu, 2 Oct 2025 15:11:03 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH 7/8] media: iris: Introduce vpu ops for vpu4 with necessary hooks Content-Language: en-US To: Vishnu Reddy , Konrad Dybcio , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250925-knp_video-v1-0-e323c0b3c0cd@oss.qualcomm.com> <20250925-knp_video-v1-7-e323c0b3c0cd@oss.qualcomm.com> <3355306e-4059-4af5-8865-3b5335356382@oss.qualcomm.com> <68686586-f161-c6c6-cd3f-c5eb87e33954@quicinc.com> From: Vikash Garodia In-Reply-To: <68686586-f161-c6c6-cd3f-c5eb87e33954@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=RZKdyltv c=1 sm=1 tr=0 ts=68de48b7 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=COk6AnOGAAAA:8 a=EUspDBNiAAAA:8 a=bkvKUzPmFnKcqkYD6asA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=rl5im9kqc5Lf4LNbBjHf:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: mikWBb_ZFBqduVagWG92OiCMtMmXuHhw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTI3MDAzMyBTYWx0ZWRfX3/Hxfmqt3jbU pDL2syySJvcqA7I8aX8dyZx+AypEtQVT414mQoUWo/NVoRBJSdHW641TAgfbSYIbRIbQyImR7uA m2HSY3EgIfkDBdflfdLBh4FnMTTQNymk9mGvSxImLIKbhmp0vyfQEO83mrS+QWUtQSqpX3zm9Um a6k/rHZJ7u1UFLV8JTDJm/uuqj8UXAreAm9COSwk2UuWTF19RquRdtK7D6GJJHfgJPe9sHajIwE O70K5E8JSe/060rZtIolNA9v7GGqYBjVZMUewI3827uncsP4F3fwZLZ8y+6tITA2Rk4Zxj9O8SC 6TQmDF/k2Q6Wsn810c3sqoCNsDK36zDXxS6faVlozupEZpLZANgF7Q52fCCjUhp3FQEZ6qiXdl/ wPmQLWrlRyW4hOnE38vvxF3LTVaBZg== X-Proofpoint-ORIG-GUID: mikWBb_ZFBqduVagWG92OiCMtMmXuHhw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-02_03,2025-10-02_02,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 priorityscore=1501 adultscore=0 phishscore=0 impostorscore=0 spamscore=0 bulkscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2509150000 definitions=main-2509270033 On 9/29/2025 11:15 AM, Vishnu Reddy wrote: > > > On 9/25/2025 2:48 PM, Konrad Dybcio wrote: >> On 9/25/25 1:14 AM, Vikash Garodia wrote: >>> Add power sequence for vpu4 by reusing from previous generation wherever >>> possible. Hook up vpu4 op with vpu4 specific implemtation or resue from >>> earlier generation wherever feasible, like clock calculation in this >>> case. >>> >>> Co-developed-by: Vishnu Reddy >>> Signed-off-by: Vishnu Reddy >>> Signed-off-by: Vikash Garodia >>> --- >> >> [...] >> >>> +#include >>> +#include >>> +#include "iris_instance.h" >>> +#include "iris_vpu_common.h" >>> +#include "iris_vpu_register_defines.h" >>> + >>> +#define WRAPPER_EFUSE_MONITOR            (WRAPPER_BASE_OFFS + 0x08) >>> +#define AON_WRAPPER_MVP_NOC_RESET_SYNCRST    (AON_MVP_NOC_RESET + 0x08) >>> +#define CPU_CS_APV_BRIDGE_SYNC_RESET        (CPU_BASE_OFFS + 0x174) >>> +#define DISABLE_VIDEO_APV_BIT            BIT(27) >>> +#define DISABLE_VIDEO_VPP1_BIT            BIT(28) >>> +#define DISABLE_VIDEO_VPP0_BIT            BIT(29) >>> +#define CORE_CLK_HALT                BIT(0) >>> +#define APV_CLK_HALT                BIT(1) >>> +#define CORE_PWR_ON                BIT(1) >>> + >>> +static int iris_vpu4x_genpd_set_hwmode(struct iris_core *core, bool hw_mode) >>> +{ >>> +    u32 value = readl(core->reg_base + WRAPPER_EFUSE_MONITOR); >> >> I think this could use some explanations. >> >> I'll go ahead and assume that the eFuse tells us that parts of the >> IP are disables (hopefully not all three at once.. we shouldn't >> advertise the v4l2 device then, probably) >> >> You read back the fuse register a lot, even though I presume it's not >> supposed to change at runtime. How about we add: >> >> bool vpp0_fused_off >> bool vpp1_fused_off >> bool apv_fused_off >> >> instead? >> > >  Hi Konrad, Thanks for your review and suggestion. > >  The poweroff and poweron ops will be called in each test. There is no >  ops available that called onetime only to cache these values. >  And, to create any variable, Need to add as static global in this file >  because these are specific to this platform and I feel it's not >  recommended code to add into any common structures as a member. > >  Do you have any suggestion from your side how this can be do it in a >  simple way? IMO, its a fair point from Konrad to avoid register read multiple times. We will recheck this and optimize it to the extent possible. Regards, Vikash