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Thu, 28 May 2026 01:00:06 -0700 From: Nicolin Chen To: , , CC: , , , , , , , , , , , , , , Subject: [PATCH v2 07/11] iommu/arm-smmu-v3: Disable PRI when no IRQ handler is registered Date: Thu, 28 May 2026 00:59:35 -0700 Message-ID: <9b99c4ae66653e49b849dbca0ed2caee1cceb368.1779944354.git.nicolinc@nvidia.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4F:EE_|SA3PR12MB7949:EE_ X-MS-Office365-Filtering-Correlation-Id: 811f915a-20b6-4470-676f-08debc8f3233 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|376014|36860700016|7416014|22082099003|18002099003|6133799003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: dVNwhdcj/kXExzxYRbOPFsdQTfcwfT3A4jMikfMDEQipJlqdBXEKCv0yYbtrF9BRrwpwA8ARQUKGM61AATsUcN/Si83hIYCD7LwY5/KexxXiPkhR2oJXB3b8fL5mzo/QAGqWR+XypgWzhD1CIIoNiNuoJIlPJw/O/XdoilMcVKOBVnwzBz+v4hxRp+yecCITp/vrWdxByii57WJRTQaCB6VBXw0FKTONoSN0i30QgagtWxVLcDwnQ31eoXtHUvq9b/5L/v5vDWMImECQDA4TRofW2AXRx/Q3cyl6RPl92DhX4bWUZ28rt/B0LTFaHdnyBbHBTcGosZ1Tc6RNWQYK3dKUaj5f1PVBil3WvHod7EqNm/jYTgvzlIDu59bHCKBvIk7+sV2DfuYSkZMWOuMGxD5n/G0zzV9ojf3amvtSK0bDKaaLfbty4BOhuSePrHiS0AKH4DbHvkJinrlX13EHscw9oDgBZIfSH56SOq+kTZT3x0W8Ri7s6t7Sn1cde5rliVEQ3bubrsQnxLpp7iBNp0WsQNzIa7wAL4w93dghPB7iPDcWiqDDf+y6KhWJb2nv1Gs7naup4DETPKPdoBrhr7RRorW4BY/CXVrPeYhbdmHjEVpjLUKiNBfUHdNfcBjHBAGpY2gUlLxbVmAU5N+Etz4+jjK/nnTFhwPjhx3zkieE7k+76VZ1VgV63T3eHXZDe2tdrmv0r4H246prPP1Ii+QVHh7r1s1fsvnQA2PXA0Y= X-Forefront-Antispam-Report: CIP:216.228.117.160;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge1.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(376014)(36860700016)(7416014)(22082099003)(18002099003)(6133799003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: fqVrEiGqKEo4zo9KxYJEB70W+mV9kY/Ml+TcB46lBfqtB9vFMWkI1wUuHsJDa7WNSiTZnjVySSXKcUJeL5ToEXEVURmojndzcinIM4zpazDqBxD1TkKLKmTir+5WPhO4+yXYQAXhpIGR6HRojbS0RxsBfkWpa7d9Ai3KfE+2AY7Y3C4URN343ZoOhFwzqpe1/zyyOFpVnZyaKa4zHT5uLZCaD8/T+yTuWLqNjL+j3Bw4rab0Bfw9auDuWAEVAib6o4DA2/PV+1rkZAPtilcg04N6XF4fmM6VI9ktWJ3FS4pPdNwvFQqbi7GtjJqDXriYmKoH/sblEa16pdTNQfd6JbdGXbUj0w+TnajEisBKsWfIZrgi1omSpYQkkMmHPR7hY2LSLnLQLDtPbu1CeJ7AOlDVDWN8nwPobghdTGUPR4D2sZN+VZUOqegn1ER8DTxU X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 May 2026 08:00:34.0306 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 811f915a-20b6-4470-676f-08debc8f3233 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4F.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7949 arm_smmu_setup_irqs() has three failure paths that leave the priq without a handler: a missing priq IRQ line, devm_request_threaded_irq() failure on the priq IRQ, and devm_request_threaded_irq() failure on the combined IRQ. Each path warned but kept ARM_SMMU_FEAT_PRI set in smmu->features. With FEAT_PRI still set, arm_smmu_probe_device() calls pci_enable_pri() on PCIe endpoints, which then issue PRI Page Requests that pile up in a priq with no drainer; arm_smmu_setup_irqs() also enables IRQ_CTRL_PRIQ_IRQEN against a handler that does not exist. Separately, arm_smmu_device_reset() has already enabled CR0_PRIQEN before calling arm_smmu_setup_irqs(), so the hardware queue stays enabled regardless of what setup_irqs decides. Clear ARM_SMMU_FEAT_PRI from all three failure paths so subsequent code treats PRI as unavailable. And disable CR0_PRIQEN after the setup function returns. Assisted-by: Claude:claude-opus-4-7 Signed-off-by: Nicolin Chen --- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c index 371a8bbdf6756..72fd5caa27368 100644 --- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c @@ -4738,11 +4738,14 @@ static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) IRQF_ONESHOT, "arm-smmu-v3-priq", smmu); - if (ret < 0) + if (ret < 0) { dev_warn(smmu->dev, "failed to enable priq irq\n"); + smmu->features &= ~ARM_SMMU_FEAT_PRI; + } } else { dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); + smmu->features &= ~ARM_SMMU_FEAT_PRI; } } } @@ -4771,8 +4774,10 @@ static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) arm_smmu_combined_irq_thread, IRQF_ONESHOT, "arm-smmu-v3-combined-irq", smmu); - if (ret < 0) + if (ret < 0) { dev_warn(smmu->dev, "failed to enable combined irq\n"); + smmu->features &= ~ARM_SMMU_FEAT_PRI; + } } else arm_smmu_setup_unique_irqs(smmu); @@ -4931,6 +4936,10 @@ static int arm_smmu_device_reset(struct arm_smmu_device *smmu) return ret; } + /* arm_smmu_setup_irqs() might have unset the ARM_SMMU_FEAT_PRI */ + if (!(smmu->features & ARM_SMMU_FEAT_PRI)) + enables &= ~CR0_PRIQEN; + if (is_kdump_kernel()) enables &= ~(CR0_EVTQEN | CR0_PRIQEN); -- 2.43.0