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([2001:8a0:d6cd:9000:86f4:4e71:9fc8:3183]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48448ed38cfsm8301961f8f.19.2026.09.02.15.15.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 02 Sep 2026 15:15:25 -0700 (PDT) Message-ID: <9bb0ee66-d313-4a07-af4c-ffd002b55dee@reactivated.net> Date: Wed, 2 Sep 2026 23:15:23 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/5] iommu: Add Broadcom BCM2712 IOMMU driver To: "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Broadcom internal kernel review list Cc: iommu@lists.linux.dev, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-rpi-kernel@lists.infradead.org, linux-arm-kernel@lists.infradead.org, nick.hollinghurst@raspberrypi.com, james.quinlan@broadcom.com, Jason Gunthorpe References: <20260902-bcm2712-iommu-submit-v4-0-9dbb657578c1@reactivated.net> <20260902-bcm2712-iommu-submit-v4-4-9dbb657578c1@reactivated.net> Content-Language: en-US From: Daniel Drake In-Reply-To: <20260902-bcm2712-iommu-submit-v4-4-9dbb657578c1@reactivated.net> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 02/09/2026 18:57, Daniel Drake wrote: > +static int bcm2712_iommu_blocking_attach(struct iommu_domain *blocking_domain, > + struct device *dev, > + struct iommu_domain *old) > +{ > + struct bcm2712_iommu *mmu = dev_iommu_priv_get(dev); > + int ret = 0; > + > + scoped_guard(spinlock_irqsave, &mmu->hw_lock) { > + /* > + * Completely block DMA by disabling both the bypass window > + * and the translation aperture. > + */ > + bcm2712_iommu_writel(mmu, MMMU_BYPASS_START_OFFSET, 0); > + bcm2712_iommu_writel(mmu, MMMU_BYPASS_END_OFFSET, 0); > + bcm2712_iommu_writel(mmu, MMMU_ADDR_CAP_OFFSET, > + MMMU_ADDR_CAP_ENABLE); > + bcm2712_iommu_writel(mmu, MMMU_ILLEGAL_ADR_OFFSET, 0); > + ret = bcm2712_iommu_clear_and_enable(mmu); > + mmu->domain = NULL; > + } My understanding is that when the IOMMU is enabled, the address cap represents the highest permittable memory address; requests for anything higher would abort. So I had hoped to achieve blocking mode by setting ENABLE | 0 in ADDR_CAP, thinking that would set a cap of 0, and hence memory accesses would fail. But a Sashiko review pointed out that actually this value would produce a translation aperture of 256MB, because of the way the register works. And I confirmed this experimentally, Sashiko is right. I also confirmed experimentally that setting value 0 to ADDR_CAP (i.e. dropping the enable bit too), with the IOMMU enabled, results in a full unrestricted bypass/identity mode. So unless someone from RPi/Broadcom can inform otherwise, I'm going to conclude that the hardware doesn't support blocking mode and remove the blocking domain implementation. This will cause the iommu layer to fall back to creating an empty paging domain when blocking mode is requested, which seems appropriate if the hardware doesn't offer a more direct way of blocking all memory access. Daniel