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[88.156.142.199]) by smtp.gmail.com with ESMTPSA id o4-20020ac25e24000000b0049c86ca95bfsm1198271lfg.52.2022.11.07.03.33.33 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Nov 2022 03:33:34 -0800 (PST) Message-ID: <9bcefe53-5ac8-5265-a0ac-83cdd69798eb@linaro.org> Date: Mon, 7 Nov 2022 12:33:32 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH 2/2] dt-bindings: interrupt-controller: add yaml for LoongArch CPU interrupt controller Content-Language: en-US To: Liu Peibao , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Huacai Chen , WANG Xuerui Cc: Jianmin Lv , Yinbo Zhu , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org References: <20221107023404.26730-1-liupeibao@loongson.cn> <20221107023404.26730-2-liupeibao@loongson.cn> <196e80d8-f4fb-7393-81a5-bca757c805f5@loongson.cn> From: Krzysztof Kozlowski In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 07/11/2022 12:20, Liu Peibao wrote: > On 11/7/22 5:55 PM, Krzysztof Kozlowski wrote: >> On 07/11/2022 10:21, Liu Peibao wrote: >>> On 11/7/22 4:28 PM, Krzysztof Kozlowski wrote: >>>> On 07/11/2022 03:34, Liu Peibao wrote: >>>> >>>> Add commit msg explaining what you are doing here (e.g. the hardware). >>>> >>> >>> I just add this yaml for what I did in patch 1/2 and the header seems enough >>> to describe what I want to, so I did not add the commit log. >> >> This should instead describe briefly the hardware here. >> > > How about I add the following comments: > > "Current LoongArch compatible CPUs support 14 CPU IRQs. We can describe how > the 14 IRQs are wired to the platforms internal interrupt controller cascade > by devicetree." Sure. >>>>> + const: loongarch,cpu-interrupt-controller >>>> >>>> You have exactly one and only one type of CPU interrupt controller for >>>> all your Loongarch designs? All current and all future? All? >>>> >>> >>> It is sure of that "all current and recent designs". It is really hard to limit the >>> design in the distant future. >>> >>> And if there is updating, maybe I will add additional things like this: >>> "loongarch,cpu-interrupt-controller-2.0". >> >> Unless you have a clear versioning of your hardware, adding 2.0 won't be >> correct. Don't you have this for specific SoC? >> > > The "loongarch,cpu-interrupt-controller" now is compatible for all the LoongArch > compatible CPUs, not specific for one chip. And we may keep this CPU interrupt > controller for a long time. Still specific compatibles (as fallbacks) are used for such cases, so why is this different? Hardware compatible with several other devices still gets specific compatible, right? You cannot have "-2.0" suffix in the future just because "you want", so be sure that your choice is reasonable. Best regards, Krzysztof