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Wed, 01 Apr 2026 05:37:34 -0700 (PDT) X-Received: by 2002:a05:6300:2189:b0:398:98f2:743d with SMTP id adf61e73a8af0-39ef77862bemr3431607637.57.1775047053723; Wed, 01 Apr 2026 05:37:33 -0700 (PDT) Received: from [10.0.0.3] ([106.222.233.247]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-c769179e30dsm12438450a12.20.2026.04.01.05.37.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Apr 2026 05:37:33 -0700 (PDT) Message-ID: <9bfaf15e-99c8-a98e-d0df-9df86872bfe8@oss.qualcomm.com> Date: Wed, 1 Apr 2026 18:07:27 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:102.0) Gecko/20100101 Thunderbird/102.15.1 Subject: Re: [PATCH v4 2/5] media: iris: Add hardware power on/off ops for X1P42100 Content-Language: en-US To: Wangao Wang , Bryan O'Donoghue , Vikash Garodia , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260401-enable_iris_on_purwa-v4-0-ca784552a3e9@oss.qualcomm.com> <20260401-enable_iris_on_purwa-v4-2-ca784552a3e9@oss.qualcomm.com> From: Dikshita Agarwal In-Reply-To: <20260401-enable_iris_on_purwa-v4-2-ca784552a3e9@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDAxMDExNSBTYWx0ZWRfXwOX+o4w+D+NW DjY9rKAXvniMN+OYqOxwXeQoalimnGLhDLhkXfH5oYMJfpggu3dgsoupJkUBILlbQkN6+WDfyeE DM2WbLSdK1ywLUm1YIWB0DfBFQ0HsZfR3pIYjHQBVi+cZU6dp5BBCy7hdhujwJ8ySGvlreq0vW+ DPi0tdzw52JNlpxn6eGc69icY/TGhRAeVTwIplK/Nm/8znZyla3xlE1Z7Pc0BgwA6V5zl6bAoGv RJa7xYB6FM3AKpmddmg61SyRON82L3VQ8KUFHgDzwxo1vX9sKQ5fu5AySuPasLJeRu6lbM0Ad0O v/RDx64TxLNpJj6CGGJ78Jv+bBXSPwlSc4wNtFzJyX/eJI32RFekKFYUz8ea/4sewp1rMhGl4Z4 SVB8CZUsicJiOVh6SqtPSykLN3aCRZENWIc999BjkxpdO0O8q1XEArY9s5vAgSFlywco0abNHik eaRbw04E0ow7t2DsGvg== X-Authority-Analysis: v=2.4 cv=YcawJgRf c=1 sm=1 tr=0 ts=69cd118f cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=5/Y9Gi2N1OwmQbPtUd2E/A==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=dXMAQJrOHHfgTcScUBoA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: kueEyr3v-NVGqCyRL5snuMrAVSw7JKsW X-Proofpoint-ORIG-GUID: kueEyr3v-NVGqCyRL5snuMrAVSw7JKsW X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-01_04,2026-04-01_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 priorityscore=1501 adultscore=0 clxscore=1015 suspectscore=0 malwarescore=0 impostorscore=0 spamscore=0 lowpriorityscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2604010115 On 4/1/2026 3:54 PM, Wangao Wang wrote: > On X1P42100 the Iris block has an extra BSE clock. Wire this clock into > the power on/off sequence. > > The BSE clock is used to drive the Bin Stream Engine, which is a sub-block > of the video codec hardware responsible for bitstream-level processing. It > is required to be enabled separately from the core clock to ensure proper > codec operation. > > Signed-off-by: Wangao Wang > --- > drivers/media/platform/qcom/iris/iris_vpu3x.c | 46 ++++++++++++++++++++++ > drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + > 2 files changed, 47 insertions(+) > > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c > index fe4423b951b1e9e31d06dffc69d18071cc985731..e6a62b3ca78efeefa2eed267636789a6b405689f 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c > @@ -71,6 +71,44 @@ static void iris_vpu3_power_off_hardware(struct iris_core *core) > iris_vpu_power_off_hw(core); > } > > +static int iris_vpu3_purwa_power_on_hw(struct iris_core *core) > +{ > + int ret; > + > + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); > + if (ret) > + return ret; > + > + ret = iris_prepare_enable_clock(core, IRIS_HW_CLK); > + if (ret) > + goto err_disable_power; > + > + ret = iris_prepare_enable_clock(core, IRIS_BSE_HW_CLK); > + if (ret) > + goto err_disable_hw_clock; > + > + ret = dev_pm_genpd_set_hwmode(core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN], true); > + if (ret) > + goto err_disable_bse_hw_clock; > + > + return 0; > + > +err_disable_bse_hw_clock: > + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); > +err_disable_hw_clock: > + iris_disable_unprepare_clock(core, IRIS_HW_CLK); > +err_disable_power: > + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_HW_POWER_DOMAIN]); > + > + return ret; > +} > + > +static void iris_vpu3_purwa_power_off_hardware(struct iris_core *core) > +{ > + iris_vpu3_power_off_hardware(core); this will eventually call iris_vpu_power_off_hw which would try to disable IRIS_HW_AHB_CLK which is not applicable to purwa I think, will that not create any issue? Other than this, change LGTM. Thanks, Dikshita > + iris_disable_unprepare_clock(core, IRIS_BSE_HW_CLK); > +} > + > static void iris_vpu33_power_off_hardware(struct iris_core *core) > { > bool handshake_done = false, handshake_busy = false; > @@ -268,6 +306,14 @@ const struct vpu_ops iris_vpu3_ops = { > .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, > }; > > +const struct vpu_ops iris_vpu3_purwa_ops = { > + .power_off_hw = iris_vpu3_purwa_power_off_hardware, > + .power_on_hw = iris_vpu3_purwa_power_on_hw, > + .power_off_controller = iris_vpu_power_off_controller, > + .power_on_controller = iris_vpu_power_on_controller, > + .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, > +}; > + > const struct vpu_ops iris_vpu33_ops = { > .power_off_hw = iris_vpu33_power_off_hardware, > .power_on_hw = iris_vpu_power_on_hw, > diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h > index f6dffc613b822341fb21e12de6b1395202f62cde..88a23cbdc06c5b38b4c8db67718cbd538f0e0721 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h > +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h > @@ -10,6 +10,7 @@ struct iris_core; > > extern const struct vpu_ops iris_vpu2_ops; > extern const struct vpu_ops iris_vpu3_ops; > +extern const struct vpu_ops iris_vpu3_purwa_ops; > extern const struct vpu_ops iris_vpu33_ops; > extern const struct vpu_ops iris_vpu35_ops; > extern const struct vpu_ops iris_vpu4x_ops; >