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([2a01:e0a:982:cbb0:c728:ed22:3bb8:f351]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e47b7d12sm4510432f8f.58.2025.02.28.00.07.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Feb 2025 00:07:52 -0800 (PST) Message-ID: <9c15f084-ea4b-48e4-add6-c5b0c6de1155@linaro.org> Date: Fri, 28 Feb 2025 09:07:51 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Neil Armstrong Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH v3 1/3] arm64: dts: qcom: sm8650: fix PMU interrupt flag To: Stephan Gerhold , Konrad Dybcio Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250227-topic-sm8650-pmu-ppi-partition-v3-0-0f6feeefe50f@linaro.org> <20250227-topic-sm8650-pmu-ppi-partition-v3-1-0f6feeefe50f@linaro.org> <7535057b-b6fc-4831-ac5b-b68903083747@oss.qualcomm.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 27/02/2025 19:48, Stephan Gerhold wrote: > On Thu, Feb 27, 2025 at 06:50:31PM +0100, Konrad Dybcio wrote: >> On 27.02.2025 5:04 PM, Neil Armstrong wrote: >>> The ARM PMU interrupt is sometimes defined as IRQ_TYPE_LEVEL_LOW, >>> or IRQ_TYPE_LEVEL_HIGH, but downstream and recent platforms used the >>> IRQ_TYPE_LEVEL_HIGH flag so align the SM8650 definition to have a >>> functional PMU working. >>> >>> Fixes: c8a346e408cb ("arm64: dts: qcom: Split PMU nodes for heterogeneous CPUs") >>> Fixes: d2350377997f ("arm64: dts: qcom: add initial SM8650 dtsi") >>> Signed-off-by: Neil Armstrong >>> --- >> >> I couldn't find anything to back this up, not inside, not on Arm's >> website, but downstream agrees, so.. >> > > The GIC doesn't really have a notion of LOW vs HIGH in the programmable > registers. This is generally a design time parameter, e.g. for GIC-600: > > Level-sensitive PPI signals are active-LOW by default, as with > previous Arm GIC implementations. However, individual PPI signals can > be inverted and synchronized using parameters > gic600__PPI___. > > https://developer.arm.com/documentation/100336/0106/components-and-configuration/redistributor/redistributor-ppi-signals > > For Linux it shouldn't really matter, because gic_configure_irq() > ignores the polarity and looks only at IRQ_TYPE_LEVEL_MASK. > > If you still want this to represent the actual truth, then all hints > I can find only back this down (not up) I'm afraid: > > Arm® Cortex®‑A520 Core Technical Reference Manual > Arm® Cortex®-A720 Core Technical Reference Manual > Arm® Cortex®-X4 Core Technical Reference Manual > > 17.2 Performance monitors interrupts > When the PMU generates an interrupt, the nPMUIRQ[n] output is driven LOW. > > https://developer.arm.com/documentation/102517/0004/Performance-Monitors-Extension-support-/Performance-monitors-interrupts > https://developer.arm.com/documentation/102530/0002/Performance-Monitors-Extension-support-/Performance-monitors-interrupts > https://developer.arm.com/documentation/102484/0003/Performance-Monitors-Extension-support-/Performance-monitors-interrupts > > So please check if this patch is really needed, otherwise I'd suggest > dropping it. Thanks a lot for looking into this ! I guess I'll drop this, and we may harmonize all qcom dtsi with LOW. Neil > > Thanks, > Stephan