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When the CPU reads one of those aic7880 registers and issues another uncached load right after it, the second load sometimes returns the first one's data instead of its own: readb() of HCNTRL returns 0x02, and the readb() that follows returns 0x02 as well. The second read does not have to go to the same chip; the other aic7880 and MACE's MAC_CTRL get the stale data too. It only shows up with audio and SCSI DMA running, a few hundred times in 25 million read pairs. A gap of 2us between the two loads cures it, masking interrupts alone does not. CRIME 1.4 does not do it, and IRIX also delays around each PCI PIO read on CRIME 1.1. I'll reword that paragraph in a v2. Thanks, Imre