From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE, SPF_PASS,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9306DC5519F for ; Fri, 20 Nov 2020 10:15:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2D2C5222BA for ; Fri, 20 Nov 2020 10:15:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727426AbgKTKOx (ORCPT ); Fri, 20 Nov 2020 05:14:53 -0500 Received: from foss.arm.com ([217.140.110.172]:46614 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726172AbgKTKOw (ORCPT ); Fri, 20 Nov 2020 05:14:52 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 830031042; Fri, 20 Nov 2020 02:14:51 -0800 (PST) Received: from [10.57.26.201] (unknown [10.57.26.201]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B19D03F70D; Fri, 20 Nov 2020 02:14:49 -0800 (PST) Subject: Re: AMU extension v1 support for cortex A76, A77, A78 CPUs To: Marc Zyngier Cc: Neeraj Upadhyay , mark.rutland@arm.com, suzuki.poulose@arm.com, ionela.voinescu@arm.com, MSM , lkml , catalin.marinas@arm.com, Will Deacon , valentin.schneider@arm.com, linux-arm-kernel@lists.infradead.org References: <2cc9dd44-0b4b-94a8-155a-7a2446a1b892@codeaurora.org> <1712842eb0767e51155a5396d282102c@kernel.org> From: Vladimir Murzin Message-ID: <9c504d04-8d20-91cb-6284-2891589eff37@arm.com> Date: Fri, 20 Nov 2020 10:14:50 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 11/20/20 9:54 AM, Marc Zyngier wrote: > On 2020-11-20 09:09, Vladimir Murzin wrote: >> On 11/20/20 8:56 AM, Marc Zyngier wrote: >>> On 2020-11-20 04:30, Neeraj Upadhyay wrote: >>>> Hi, >>>> >>>> For ARM cortex A76, A77, A78 cores (which as per TRM, support AMU) >>>> AA64PFR0[47:44] field is not set, and AMU does not get enabled for >>>> them. >>>> Can you please provide support for these CPUs in cpufeature.c? >>> >>> If that was the case, that'd be an erratum, and it would need to be >>> documented as such. It could also be that this is an optional feature >>> for these cores (though the TRM doesn't suggest that). >>> >>> Can someone at ARM confirm what is the expected behaviour of these CPUs? >> >> Not a confirmation, but IIRC, these are imp def features, while our cpufeatures >> catches architected one. > > Ah, good point. So these CPUs implement some sort of AMU, and not *the* AMU. > > Yet the register names are the same. Who thought that'd be a good idea? IMO, it is the case where imp def has been generalized into arch extension, so something have been moved over. Cheers Vladimir > >         M.