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Thunderbird Subject: Re: [PATCH 3/6] platform/x86/uniwill: Implement cTGP setting To: Werner Sembach , hansg@kernel.org, ilpo.jarvinen@linux.intel.com Cc: platform-driver-x86@vger.kernel.org, linux-kernel@vger.kernel.org References: <20251117132530.32460-1-wse@tuxedocomputers.com> <20251117132530.32460-4-wse@tuxedocomputers.com> Content-Language: en-US From: Armin Wolf In-Reply-To: <20251117132530.32460-4-wse@tuxedocomputers.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-Provags-ID: V03:K1:LHusJaBNy4lEl9D+91VuCA1SwCL2YFVy/Lf13Yp1pogoaSwH/QT N8rtbyeI+7KZVRLE647gBGqUYE4SyWzwrNRHBsPH5EJ8qGPgaZsOv7nMYI1ufagUDmDTI2l /r/zuksaCJdK2RemycVWqHgA0KaovYazTKPn2TioWeNbsUxeRWm9o/IJkn5feG/67Phs3AM XA55tDjkJ54gFmhjkwIFA== X-Spam-Flag: NO UI-OutboundReport: notjunk:1;M01:P0:P3qzOTcBaQw=;JgGUGgztQwndhkzv2TIQFW5TPCN ciJnrJb8BoSrhKFEueSilWaIchC6BUEAZS/HMmVYcWcPJfebLiJbr0BJ2qj0dUzKUZbndXFTh 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i12foQ9r4Q+S/N6nbHP9oTmriltIUm9sKfqp7sgSNgzKmY9LCvjUYDg1s5vGzRMgLnBtzvCgy Pvu04kQo+m4HgDw1OGRdM4WEAveAp5AU4ABMTbdjeMO6rrjVJ9bUJHqwuj5ZMNJmeXtHDkVRJ 4LOCEpCVMWVQGkMlW4DQJEt43X46BqJ0jL1Rh1bl4nCvHyjTM19wqekjbWD+8KL33y3V8uxP4 lTL6+2GNE1YR0aJ3pmx4mn5DfjxS79v4SOuiN+l/bqBADzLjgVmCco1hdLQKRzffB56hj3CSq EzGlSgJg0qr1s0IvttcnJY0n0m+iImzVqKIR3dRAexoTWjmNu5SAIfN/baVTUhi1AXXAgwqTV ojT9K4DibanPpUNt9818ekQAysmyvQbytQ3iLHgY5nIsWGwUrVf2JyUZGmRfKMqJOEYkE7B7l MlYMAktEnsrGl1X4kpeaC5kXvsPq7AQauk4NdA9xPeweML3vFLw== Am 17.11.25 um 14:24 schrieb Werner Sembach: > Uniwill offers user setable cTGP for their EC on devices using NVIDIA 30= 00 > Series and newer GPUs. This patch implements this setting as a sysfs > attribute. > > Signed-off-by: Werner Sembach > --- > drivers/platform/x86/uniwill/uniwill-acpi.c | 110 +++++++++++++++++++- > 1 file changed, 107 insertions(+), 3 deletions(-) > > diff --git a/drivers/platform/x86/uniwill/uniwill-acpi.c b/drivers/platf= orm/x86/uniwill/uniwill-acpi.c > index 0cb86a701b2e1..de3417d9d1ac0 100644 > --- a/drivers/platform/x86/uniwill/uniwill-acpi.c > +++ b/drivers/platform/x86/uniwill/uniwill-acpi.c > @@ -122,11 +122,11 @@ > #define CTGP_DB_DB_ENABLE BIT(1) > #define CTGP_DB_CTGP_ENABLE BIT(2) > =20 > -#define EC_ADDR_CTGP_OFFSET 0x0744 > +#define EC_ADDR_CTGP_DB_CTGP_OFFSET 0x0744 > =20 > -#define EC_ADDR_TPP_OFFSET 0x0745 > +#define EC_ADDR_CTGP_DB_TPP_OFFSET 0x0745 > =20 > -#define EC_ADDR_MAX_TGP 0x0746 > +#define EC_ADDR_CTGP_DB_DB_OFFSET 0x0746 > =20 > #define EC_ADDR_LIGHTBAR_AC_CTRL 0x0748 > #define LIGHTBAR_APP_EXISTS BIT(0) > @@ -317,6 +317,7 @@ > #define UNIWILL_FEATURE_LIGHTBAR BIT(3) > #define UNIWILL_FEATURE_BATTERY BIT(4) > #define UNIWILL_FEATURE_HWMON BIT(5) > +#define UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL BIT(6) > =20 > struct uniwill_data { > struct device *dev; > @@ -498,6 +499,10 @@ static bool uniwill_writeable_reg(struct device *de= v, unsigned int reg) > case EC_ADDR_LIGHTBAR_BAT_RED: > case EC_ADDR_LIGHTBAR_BAT_GREEN: > case EC_ADDR_LIGHTBAR_BAT_BLUE: > + case EC_ADDR_CTGP_DB_CTRL: > + case EC_ADDR_CTGP_DB_CTGP_OFFSET: > + case EC_ADDR_CTGP_DB_TPP_OFFSET: > + case EC_ADDR_CTGP_DB_DB_OFFSET: > return true; > default: > return false; > @@ -531,6 +536,10 @@ static bool uniwill_readable_reg(struct device *dev= , unsigned int reg) > case EC_ADDR_LIGHTBAR_BAT_RED: > case EC_ADDR_LIGHTBAR_BAT_GREEN: > case EC_ADDR_LIGHTBAR_BAT_BLUE: > + case EC_ADDR_CTGP_DB_CTRL: > + case EC_ADDR_CTGP_DB_CTGP_OFFSET: > + case EC_ADDR_CTGP_DB_TPP_OFFSET: > + case EC_ADDR_CTGP_DB_DB_OFFSET: > return true; > default: > return false; > @@ -786,6 +795,68 @@ static ssize_t breathing_in_suspend_show(struct dev= ice *dev, struct device_attri > =20 > static DEVICE_ATTR_RW(breathing_in_suspend); > =20 > +static ssize_t ctgp_offset_store(struct device *dev, struct device_attr= ibute *attr, > + const char *buf, size_t count) > +{ > + struct uniwill_data *data =3D dev_get_drvdata(dev); > + unsigned int value; > + int ret; > + > + ret =3D kstrtouint(buf, 0, &value); > + if (ret < 0) > + return ret; > + > + ret =3D regmap_write(data->regmap, EC_ADDR_CTGP_DB_CTGP_OFFSET, value)= ; > + if (ret < 0) > + return ret; > + > + return count; > +} > + > +static ssize_t ctgp_offset_show(struct device *dev, struct device_attri= bute *attr, > + char *buf) > +{ > + struct uniwill_data *data =3D dev_get_drvdata(dev); > + unsigned int value; > + int ret; > + > + ret =3D regmap_read(data->regmap, EC_ADDR_CTGP_DB_CTGP_OFFSET, &value)= ; > + if (ret < 0) > + return ret; > + > + return sysfs_emit(buf, "%u\n", value); > +} > + > +DEVICE_ATTR_RW(ctgp_offset); > + > +static int uniwill_nvidia_ctgp_init(struct uniwill_data *data) > +{ > + int ret; > + > + if (!(supported_features & UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL)) > + return 0; > + > + ret =3D regmap_update_bits(data->regmap, EC_ADDR_CTGP_DB_CTRL, > + CTGP_DB_GENERAL_ENABLE | CTGP_DB_DB_ENABLE | CTGP_DB_CTGP_ENABLE, > + CTGP_DB_GENERAL_ENABLE | CTGP_DB_DB_ENABLE | CTGP_DB_CTGP_ENABLE); I think we should initialize the power limits before enabling them, otherw= ise the relevant registers might still contain invalid data. > + if (ret < 0) > + return ret; > + > + ret =3D regmap_write(data->regmap, EC_ADDR_CTGP_DB_CTGP_OFFSET, 0); > + if (ret < 0) > + return ret; > + > + ret =3D regmap_write(data->regmap, EC_ADDR_CTGP_DB_TPP_OFFSET, 255); > + if (ret < 0) > + return ret; > + > + ret =3D regmap_write(data->regmap, EC_ADDR_CTGP_DB_DB_OFFSET, 25); > + if (ret < 0) > + return ret; Are those values the maximum values supported by the platform? If yes then we should enforce them for sysfs writes. Also, why is only cTGP accessible from user space? Thanks, Armin Wolf > + > + return 0; > +} > + > static struct attribute *uniwill_attrs[] =3D { > /* Keyboard-related */ > &dev_attr_fn_lock_toggle_enable.attr, > @@ -794,6 +865,8 @@ static struct attribute *uniwill_attrs[] =3D { > /* Lightbar-related */ > &dev_attr_rainbow_animation.attr, > &dev_attr_breathing_in_suspend.attr, > + /* Power-management-related */ > + &dev_attr_ctgp_offset.attr, > NULL > }; > =20 > @@ -820,6 +893,11 @@ static umode_t uniwill_attr_is_visible(struct kobje= ct *kobj, struct attribute *a > return attr->mode; > } > =20 > + if (attr =3D=3D &dev_attr_ctgp_offset.attr) { > + if (supported_features & UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL) > + return attr->mode; > + } > + > return 0; > } > =20 > @@ -1371,6 +1449,10 @@ static int uniwill_probe(struct platform_device *= pdev) > if (ret < 0) > return ret; > =20 > + ret =3D uniwill_nvidia_ctgp_init(data); > + if (ret < 0) > + return ret; > + > return uniwill_input_init(data); > } > =20 > @@ -1547,6 +1629,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "PHxTQx1"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO InfinityBook Pro 14/16 Gen7 Intel", > @@ -1554,6 +1637,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "PHxARX1_PHxAQF1"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO InfinityBook Pro 16 Gen7 Intel/Commodore Omnia-Bo= ok Pro Gen 7", > @@ -1561,6 +1645,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "PH6AG01_PH6AQ71_PH6AQI1"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO InfinityBook Pro 14/16 Gen8 Intel/Commodore Omnia= -Book Pro Gen 8", > @@ -1575,6 +1660,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "PH4PG31"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO InfinityBook Pro 16 Gen8 Intel", > @@ -1582,6 +1668,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "PH6PG01_PH6PG71"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO InfinityBook Pro 14/15 Gen9 AMD", > @@ -1694,6 +1781,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxMGxx"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Polaris 15/17 Gen2 Intel", > @@ -1701,6 +1789,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxNGxx"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris/Polaris 15/17 Gen3 AMD", > @@ -1708,6 +1797,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxZGxx"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris/Polaris 15/17 Gen3 Intel", > @@ -1715,6 +1805,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxTGxx"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris/Polaris 15/17 Gen4 AMD", > @@ -1722,6 +1813,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxRGxx"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris 15 Gen4 Intel", > @@ -1729,6 +1821,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxAGxx"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Polaris 15/17 Gen5 AMD", > @@ -1736,6 +1829,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxXGxx"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris 16 Gen5 AMD", > @@ -1743,6 +1837,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GM6XGxX"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris 16/17 Gen5 Intel/Commodore ORION Gen 5"= , > @@ -1750,6 +1845,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxPXxx"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris Slim 15 Gen6 AMD", > @@ -1757,6 +1853,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GMxHGxx"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris Slim 15 Gen6 Intel/Commodore ORION Slim= 15 Gen6", > @@ -1764,6 +1861,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GM5IXxA"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris 16 Gen6 Intel/Commodore ORION 16 Gen6", > @@ -1771,6 +1869,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GM6IXxB_MB1"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris 16 Gen6 Intel/Commodore ORION 16 Gen6", > @@ -1778,6 +1877,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GM6IXxB_MB2"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris 17 Gen6 Intel/Commodore ORION 17 Gen6", > @@ -1785,6 +1885,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "GM7IXxN"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris 16 Gen7 AMD", > @@ -1792,6 +1893,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "X6FR5xxY"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris 16 Gen7 Intel", > @@ -1799,6 +1901,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "X6AR5xxY"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Stellaris 16 Gen7 Intel", > @@ -1806,6 +1909,7 @@ static const struct dmi_system_id uniwill_dmi_tabl= e[] __initconst =3D { > DMI_MATCH(DMI_SYS_VENDOR, "TUXEDO"), > DMI_EXACT_MATCH(DMI_BOARD_NAME, "X6AR5xxY_mLED"), > }, > + .driver_data =3D (void *)(UNIWILL_FEATURE_NVIDIA_CTGP_CONTROL), > }, > { > .ident =3D "TUXEDO Pulse 14 Gen1 AMD",