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b=XP9YCwwz9FDgTq9DiPDtXaQngWd++vaMBU0pw/qc8h0Tg52bq8fuemJoYDVXg6I/VxIOJwuO3wGFXyYaYbdNpe1ASJpooXAvY+hofGhIi2tstBW0vRan0Tao8sv5GIq+K79yi+wt+J9laPdmZ3W6T/wxLKkDdSNBZwDPWXumZbs= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from MW3PR12MB4553.namprd12.prod.outlook.com (2603:10b6:303:2c::19) by DS0PR12MB8415.namprd12.prod.outlook.com (2603:10b6:8:fc::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7982.27; Mon, 23 Sep 2024 15:31:02 +0000 Received: from MW3PR12MB4553.namprd12.prod.outlook.com ([fe80::b0ef:2936:fec1:3a87]) by MW3PR12MB4553.namprd12.prod.outlook.com ([fe80::b0ef:2936:fec1:3a87%4]) with mapi id 15.20.7982.022; Mon, 23 Sep 2024 15:31:02 +0000 Message-ID: <9cb5b1ad-5a7c-42a4-8207-2890f1c32e0f@amd.com> Date: Mon, 23 Sep 2024 10:30:58 -0500 User-Agent: Mozilla Thunderbird Reply-To: babu.moger@amd.com Subject: Re: [PATCH v7 06/24] x86/resctrl: Add support to enable/disable AMD ABMC feature To: Reinette Chatre , corbet@lwn.net, fenghua.yu@intel.com, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, dave.hansen@linux.intel.com Cc: x86@kernel.org, hpa@zytor.com, paulmck@kernel.org, rdunlap@infradead.org, tj@kernel.org, peterz@infradead.org, yanjiewtw@gmail.com, kim.phillips@amd.com, lukas.bulwahn@gmail.com, seanjc@google.com, jmattson@google.com, leitao@debian.org, jpoimboe@kernel.org, rick.p.edgecombe@intel.com, kirill.shutemov@linux.intel.com, jithu.joseph@intel.com, kai.huang@intel.com, kan.liang@linux.intel.com, daniel.sneddon@linux.intel.com, pbonzini@redhat.com, sandipan.das@amd.com, ilpo.jarvinen@linux.intel.com, peternewman@google.com, maciej.wieczor-retman@intel.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, eranian@google.com, james.morse@arm.com References: <556b3576ce076c8867795d4af1bcdaf883397304.1725488488.git.babu.moger@amd.com> <56f1396e-8a51-43d3-9dd0-dc55a1623b12@intel.com> Content-Language: en-US From: "Moger, Babu" In-Reply-To: <56f1396e-8a51-43d3-9dd0-dc55a1623b12@intel.com> Content-Type: text/plain; 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When the state of ABMC is changed, the MSR needs >> to be updated on all the logical processors in the QOS Domain. >> >> Hardware counters will reset when ABMC state is changed. Reset the >> architectural state maintained by resctrl so that reading of a hardware >> counter is not considered as an overflow in next update. > > Above mentions that architectural state is also reset, but that does > not seem to form part of this patch? Yes. Correct. Will remove this text. > >> >> The ABMC feature details are documented in APM listed below [1]. >> [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming >> Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth >> Monitoring (ABMC). >> >> Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 >> Signed-off-by: Babu Moger >> --- > > ... > >> static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r) >> diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >> index 7e76f8d839fc..0178555bf3f6 100644 >> --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c >> +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c >> @@ -2402,6 +2402,41 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_level l, bool enable) >> return 0; >> } >> >> +/* >> + * Update L3_QOS_EXT_CFG MSR on all the CPUs associated with the resource. > > This comment is not accurate since the function below only sets MSR on current CPU. Sure. Will move this comment to the caller where "on_each_cpu_mask" is called. > >> + */ >> +static void resctrl_abmc_set_one_amd(void *arg) > > Reinette > -- Thanks Babu Moger