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Fri, 13 Nov 2026 00:42:20 -0800 (PST) Received: from [192.168.226.72] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c5095b911desm64855966b.81.2026.11.13.00.42.18 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 13 Nov 2026 00:42:20 -0800 (PST) Message-ID: <9d0a3aec-052f-4209-b2db-0c2112de33aa@oss.qualcomm.com> Date: Fri, 13 Nov 2026 09:42:17 +0100 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/3] arm64: dts: qcom: sm8750: describe all MDSS block resets To: Qianhui Xu , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, dmitry.baryshkov@oss.qualcomm.com, abhinav.kumar@linux.dev, jesszhan0024@gmail.com, taniya.das@oss.qualcomm.com, andersson@kernel.org Cc: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa References: <8a0c75949fcf428a2163a2e63b27fcf08d3b4f9c.1794558882.git.xiaqinghuan@mail.ustc.edu.cn> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <8a0c75949fcf428a2163a2e63b27fcf08d3b4f9c.1794558882.git.xiaqinghuan@mail.ustc.edu.cn> Content-Type: text/plain; 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The > MDSS node is an interrupt controller in DT and the DPU takes its IRQ > from it, so INT2 is part of the same block, not a separate device. > > Bootloaders hand over with the display block still running, so describe > both block resets and let the MDSS reset return the whole group to a > known state before any display hardware is programmed. > > Reviewed-by: Abel Vesa > Reviewed-by: Dmitry Baryshkov > Signed-off-by: Qianhui Xu > --- Reviewed-by: Konrad Dybcio Konrad