From: Alexander Sverdlin <alexander.sverdlin@gmail.com>
To: Anshumali Gaur <agaur@marvell.com>,
"conor.dooley@microchip.com" <conor.dooley@microchip.com>,
"ulf.hansson@linaro.org" <ulf.hansson@linaro.org>,
"arnd@arndb.de" <arnd@arndb.de>,
"linus.walleij@linaro.org" <linus.walleij@linaro.org>,
"nikita.shubin@maquefel.me" <nikita.shubin@maquefel.me>,
"vkoul@kernel.org" <vkoul@kernel.org>,
"cyy@cyyself.name" <cyy@cyyself.name>,
"krzysztof.kozlowski@linaro.org" <krzysztof.kozlowski@linaro.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
Sunil Kovvuri Goutham <sgoutham@marvell.com>
Subject: Re: [PATCH 4/4] soc: marvell: rvu-pf: Handle function level reset (FLR) IRQs for VFs
Date: Wed, 25 Sep 2024 11:19:04 +0200 [thread overview]
Message-ID: <9d0bac264a62f4b5f161a53bcaca35b6cef42376.camel@gmail.com> (raw)
In-Reply-To: <DM6PR18MB3289700364A89C7714973C70B8692@DM6PR18MB3289.namprd18.prod.outlook.com>
Hi Anshumali!
On Wed, 2024-09-25 at 09:13 +0000, Anshumali Gaur wrote:
> > > +static irqreturn_t rvu_gen_pf_me_intr_handler(int irq, void *pf_irq)
> > > +{
> > > + struct gen_pf_dev *pfdev = (struct gen_pf_dev *)pf_irq;
> > > + int vf, reg, num_reg = 1;
> > > + u64 intr;
> > > +
> > > + if (pfdev->total_vfs > 64)
> > > + num_reg = 2;
> > > +
> > > + for (reg = 0; reg < num_reg; reg++) {
> > > + intr = readq(pfdev->reg_base + RVU_PF_VFME_INTX(reg));
> > > + if (!intr)
> > > + continue;
> > > + for (vf = 0; vf < 64; vf++) {
> > > + if (!(intr & BIT_ULL(vf)))
> > > + continue;
> > > + /* clear trpend bit */
> > > + writeq(BIT_ULL(vf), pfdev->reg_base +
> > RVU_PF_VFTRPENDX(reg));
> > > + /* clear interrupt */
> > > + writeq(BIT_ULL(vf), pfdev->reg_base +
> > RVU_PF_VFME_INTX(reg));
> > > + }
> > > + }
> >
> > Should anything else have been performed in the IRQ handler besides
> > acknowledging the IRQ request?
> >
> We are just acknowledging the IRQ request here.
But what's the goal of requesting the IRQ in the first place then?
--
Alexander Sverdlin.
next prev parent reply other threads:[~2024-09-25 9:19 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-20 11:23 [PATCH 0/4] soc: marvell: Add a general purpose RVU physical Anshumali Gaur
2024-09-20 11:23 ` [PATCH 1/4] soc: marvell: Add a general purpose RVU PF driver Anshumali Gaur
2024-09-20 22:30 ` Alexander Sverdlin
2024-09-21 21:38 ` Alexander Sverdlin
2024-09-20 11:23 ` [PATCH 2/4] soc: marvell: rvu-pf: Add PF to AF mailbox communication support Anshumali Gaur
2024-09-21 21:43 ` Alexander Sverdlin
2024-09-24 23:09 ` Alexander Sverdlin
2024-09-20 11:23 ` [PATCH 3/4] soc: marvell: rvu-pf: Add mailbox communication btw RVU VFs and PF Anshumali Gaur
2024-09-21 22:22 ` Alexander Sverdlin
2024-09-20 11:23 ` [PATCH 4/4] soc: marvell: rvu-pf: Handle function level reset (FLR) IRQs for VFs Anshumali Gaur
2024-09-21 22:49 ` Alexander Sverdlin
2024-09-25 9:13 ` Anshumali Gaur
2024-09-25 9:19 ` Alexander Sverdlin [this message]
2024-09-25 12:46 ` Anshumali Gaur
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