From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: Jie Gan <jie.gan@oss.qualcomm.com>,
Mike Leach <mike.leach@linaro.org>,
James Clark <james.clark@linaro.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>,
Jinlong Mao <jinlong.mao@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org
Subject: Re: [PATCH v6 3/9] coresight: tmc: add etr_buf_list to store allocated etr_buf
Date: Wed, 3 Dec 2025 16:20:47 +0000 [thread overview]
Message-ID: <9d163813-068b-4921-87fe-8e229692ba2b@arm.com> (raw)
In-Reply-To: <20250908-enable-byte-cntr-for-tmc-v6-3-1db9e621441a@oss.qualcomm.com>
On 08/09/2025 03:01, Jie Gan wrote:
> Add a list to store allocated etr_buf.
>
> The byte-cntr functionality requires two etr_buf to receive trace data.
> The active etr_buf collects the trace data from source device, while the
> byte-cntr reading function accesses the deactivated etr_buf after is
> has been filled and synced, transferring data to the userspace.
>
> Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
This patch alone doesn't make any sense. Please fold it with a proper
user (i.e. later patches). I can't make any sense of how this will be
used TBH without the following patches and on its own, it doesn't do
much anyways.
Suzuki
> ---
> drivers/hwtracing/coresight/coresight-tmc-core.c | 1 +
> drivers/hwtracing/coresight/coresight-tmc.h | 17 +++++++++++++++++
> 2 files changed, 18 insertions(+)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
> index be964656be93..4d249af93097 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
> @@ -830,6 +830,7 @@ static int __tmc_probe(struct device *dev, struct resource *res)
> idr_init(&drvdata->idr);
> mutex_init(&drvdata->idr_mutex);
> dev_list = &etr_devs;
> + INIT_LIST_HEAD(&drvdata->etr_buf_list);
> break;
> case TMC_CONFIG_TYPE_ETF:
> desc.groups = coresight_etf_groups;
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 6541a27a018e..292e25d82b62 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -208,6 +208,19 @@ struct tmc_resrv_buf {
> s64 len;
> };
>
> +/**
> + * @sysfs_buf: Allocated sysfs_buf.
> + * @is_free: Indicates whether the buffer is free to choose.
> + * @pos: Position of the buffer.
> + * @node: Node in etr_buf_list.
> + */
> +struct etr_buf_node {
> + struct etr_buf *sysfs_buf;
> + bool is_free;
> + loff_t pos;
> + struct list_head node;
> +};
> +
> /**
> * struct tmc_drvdata - specifics associated to an TMC component
> * @pclk: APB clock if present, otherwise NULL
> @@ -242,6 +255,8 @@ struct tmc_resrv_buf {
> * (after crash) by default.
> * @crash_mdata: Reserved memory for storing tmc crash metadata.
> * Used by ETR/ETF.
> + * @etr_buf_list: List that is used to manage allocated etr_buf.
> + * @reading_node: Available buffer for byte-cntr reading.
> */
> struct tmc_drvdata {
> struct clk *pclk;
> @@ -271,6 +286,8 @@ struct tmc_drvdata {
> struct etr_buf *perf_buf;
> struct tmc_resrv_buf resrv_buf;
> struct tmc_resrv_buf crash_mdata;
> + struct list_head etr_buf_list;
> + struct etr_buf_node *reading_node;
> };
>
> struct etr_buf_operations {
>
next prev parent reply other threads:[~2025-12-03 16:20 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-08 2:01 [PATCH v6 0/9] coresight: ctcu: Enable byte-cntr function for TMC ETR Jie Gan
2025-09-08 2:01 ` [PATCH v6 1/9] coresight: core: Refactoring ctcu_get_active_port and make it generic Jie Gan
2025-12-03 16:18 ` Suzuki K Poulose
2025-12-04 2:45 ` Jie Gan
2025-09-08 2:01 ` [PATCH v6 2/9] coresight: core: add a new API to retrieve the helper device Jie Gan
2025-12-03 16:15 ` Suzuki K Poulose
2025-12-04 2:47 ` Jie Gan
2025-09-08 2:01 ` [PATCH v6 3/9] coresight: tmc: add etr_buf_list to store allocated etr_buf Jie Gan
2025-12-03 14:24 ` Mike Leach
2025-12-03 16:20 ` Suzuki K Poulose [this message]
2025-09-08 2:01 ` [PATCH v6 4/9] coresight: tmc: add create/clean functions for etr_buf_list Jie Gan
2025-12-03 14:26 ` Mike Leach
2025-09-08 2:01 ` [PATCH v6 5/9] coresight: tmc: Introduce sysfs_read_ops to wrap sysfs read operations Jie Gan
2025-09-08 2:01 ` [PATCH v6 6/9] dt-bindings: arm: add an interrupt property for Coresight CTCU Jie Gan
2025-12-03 14:30 ` Mike Leach
2025-12-04 2:49 ` Jie Gan
2025-12-03 18:14 ` Suzuki K Poulose
2025-12-04 2:53 ` Jie Gan
2025-12-04 9:22 ` Suzuki K Poulose
2025-12-05 1:01 ` Jie Gan
2025-09-08 2:01 ` [PATCH v6 7/9] coresight: ctcu: enable byte-cntr for TMC ETR devices Jie Gan
2025-09-08 2:02 ` [PATCH v6 8/9] coresight: tmc: integrate byte-cntr's read_ops with sysfs file_ops Jie Gan
2025-09-08 2:02 ` [PATCH v6 9/9] arm64: dts: qcom: lemans: Add interrupts to CTCU device Jie Gan
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