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b=WPHUt4b1B1Jnku1Hodm0s7BrrhN4a6deyU96Nk86G9VBLJaEVFK4+MqN3349u6T76tffd/mxsTRfo09Mh9YPJK3CJtyTMSNmpwX5yp6dGZeREnZw8vkx4c3ujgX++Dah1OxkbypgDk9j9j+mSEztEpyr4k3E3A1pFtoeZDgAC+U= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from SJ0PR12MB5673.namprd12.prod.outlook.com (2603:10b6:a03:42b::13) by DS2PR12MB9799.namprd12.prod.outlook.com (2603:10b6:8:270::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.7; Wed, 5 Nov 2025 10:07:37 +0000 Received: from SJ0PR12MB5673.namprd12.prod.outlook.com ([fe80::ec7a:dd71:9d6c:3062]) by SJ0PR12MB5673.namprd12.prod.outlook.com ([fe80::ec7a:dd71:9d6c:3062%4]) with mapi id 15.20.9275.015; Wed, 5 Nov 2025 10:07:37 +0000 Message-ID: <9d3fb5f6-6e54-46e0-9b49-23bce4f4bfd9@amd.com> Date: Wed, 5 Nov 2025 11:07:32 +0100 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 17/20] drm/amdgpu: get rid of amdgpu_ttm_clear_buffer To: Pierre-Eric Pelloux-Prayer , Pierre-Eric Pelloux-Prayer , Alex Deucher , David Airlie , Simona Vetter , Sumit Semwal Cc: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org References: <20251104083605.13677-1-pierre-eric.pelloux-prayer@amd.com> <20251104083605.13677-18-pierre-eric.pelloux-prayer@amd.com> <9742acac-9402-4351-8cff-559ba6536629@damsy.net> Content-Language: en-US From: =?UTF-8?Q?Christian_K=C3=B6nig?= In-Reply-To: <9742acac-9402-4351-8cff-559ba6536629@damsy.net> Content-Type: text/plain; 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>>> - >>> -        r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence); >>> +        r = amdgpu_fill_buffer(NULL, bo, 0, NULL, >>> +                       NULL, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); >>>           if (unlikely(r)) >>>               goto fail_unreserve; >>> - >>> -        dma_resv_add_fence(bo->tbo.base.resv, fence, >>> -                   DMA_RESV_USAGE_KERNEL); >>> -        dma_fence_put(fence); >>>       } >>>       if (!bp->resv) >>>           amdgpu_bo_unreserve(bo); >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c >>> index d88bdb2ac083..1f553c56f31d 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c >>> @@ -2412,75 +2412,6 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, >>>       return 0; >>>   } >>>   -/** >>> - * amdgpu_ttm_clear_buffer - clear memory buffers >>> - * @bo: amdgpu buffer object >>> - * @resv: reservation object >>> - * @fence: dma_fence associated with the operation >>> - * >>> - * Clear the memory buffer resource. >>> - * >>> - * Returns: >>> - * 0 for success or a negative error code on failure. >>> - */ >>> -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, >>> -                struct dma_resv *resv, >>> -                struct dma_fence **fence) >>> -{ >>> -    struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev); >>> -    struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0]; >>> -    struct amdgpu_ttm_entity *entity; >>> -    struct amdgpu_res_cursor cursor; >>> -    u64 addr; >>> -    int r = 0; >>> - >>> -    if (!adev->mman.buffer_funcs_enabled) >>> -        return -EINVAL; >>> - >>> -    if (!fence) >>> -        return -EINVAL; >>> -    entity = &adev->mman.clear_entities[0]; >>> -    *fence = dma_fence_get_stub(); >>> - >>> -    amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor); >>> - >>> -    mutex_lock(&entity->gart_window_lock); >>> -    while (cursor.remaining) { >>> -        struct dma_fence *next = NULL; >>> -        u64 size; >>> - >>> -        if (amdgpu_res_cleared(&cursor)) { >>> -            amdgpu_res_next(&cursor, cursor.size); >>> -            continue; >>> -        } >>> - >>> -        /* Never clear more than 256MiB at once to avoid timeouts */ >>> -        size = min(cursor.size, 256ULL << 20); >>> - >>> -        r = amdgpu_ttm_map_buffer(&entity->base, >>> -                      &bo->tbo, bo->tbo.resource, &cursor, >>> -                      entity->gart_window_id1, ring, false, &size, &addr, >>> -                      NULL, NULL); >>> -        if (r) >>> -            goto err; >>> - >>> -        r = amdgpu_ttm_fill_mem(ring, &entity->base, 0, addr, size, resv, >>> -                    &next, true, >>> -                    AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER); >>> -        if (r) >>> -            goto err; >>> - >>> -        dma_fence_put(*fence); >>> -        *fence = next; >>> - >>> -        amdgpu_res_next(&cursor, size); >>> -    } >>> -err: >>> -    mutex_unlock(&entity->gart_window_lock); >>> - >>> -    return r; >>> -} >>> - >>>   /** >>>    * amdgpu_fill_buffer - fill a buffer with a given value >>>    * @entity: optional entity to use. If NULL, the clearing entities will be >>> @@ -2508,6 +2439,9 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity, >>>       struct amdgpu_res_cursor dst; >>>       uint64_t cur_size, to; >>>       int r, e, n_fences; >> >>> +    /* The clear flag is only valid directly after allocation. */ >>> +    bool consider_clear_flag = >>> +        src_data == 0 && k_job_id == AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER; >> >> Absolutely clear NAK to that. > > I suppose the NAK applies to the check, not the general idea of the patch? Correct. > In that case, would passing "bool consider_clear_flag" as a parameter be ok ? And then determining the k_job_id based on this new flag? Yeah, that sounds much cleaner. Christian. > > Pierre-Eric > >> >> Christian. >> >>>         /* The fences will be either added to the resv object or the last fence >>>        * will be returned to the caller. In the latter case, all fill jobs will >>> @@ -2531,6 +2465,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity, >>>           while (dst.remaining) { >>>               cur_size = min(dst.size, 256ULL << 20); >>>   +            if (consider_clear_flag && amdgpu_res_cleared(&dst)) { >>> +                amdgpu_res_next(&dst, dst.size); >>> +                continue; >>> +            } >>> + >>>               n_fences += 1; >>>               amdgpu_res_next(&dst, cur_size); >>>           } >>> @@ -2550,6 +2489,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity, >>>       amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst); >>>         while (dst.remaining) { >>> +        if (consider_clear_flag && amdgpu_res_cleared(&dst)) { >>> +            amdgpu_res_next(&dst, dst.size); >>> +            continue; >>> +        } >>> + >>>           /* Never fill more than 256MiB at once to avoid timeouts */ >>>           cur_size = min(dst.size, 256ULL << 20); >>>   @@ -2574,8 +2518,10 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity, >>>               goto error; >>>           } >>>   + >>>           r = amdgpu_ttm_fill_mem(ring, &entity->base, >>> -                    src_data, to, cur_size, resv, >>> +                    src_data, to, cur_size, >>> +                    resv, >>>                       &fence, true, k_job_id); >>>           if (r) { >>>               mutex_unlock(&entity->gart_window_lock); >>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h >>> index c059a3d52b57..97e73919cb0c 100644 >>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h >>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h >>> @@ -182,9 +182,6 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, >>>                  struct dma_resv *resv, >>>                  struct dma_fence **fence, >>>                  bool vm_needs_flush, uint32_t copy_flags); >>> -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo, >>> -                struct dma_resv *resv, >>> -                struct dma_fence **fence); >>>   int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity, >>>                  struct amdgpu_bo *bo, >>>                  uint32_t src_data,