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Sun, 17 Dec 2023 22:13:45 -0800 Message-ID: <9d507505-e2f4-4916-a98c-9ba67a771d77@quicinc.com> Date: Mon, 18 Dec 2023 11:43:42 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 3/5] iommu/arm-smmu: add ACTLR data and support for SM8550 Content-Language: en-US To: Dmitry Baryshkov , Konrad Dybcio , Robin Murphy CC: , , , , , , , , , , , , , , , , References: <20231215101827.30549-1-quic_bibekkum@quicinc.com> <20231215101827.30549-4-quic_bibekkum@quicinc.com> <1eee8bae-59f0-4066-9d04-8c3a5f750d3a@linaro.org> <42d627af-164b-4b50-973e-fa71d86cb84c@linaro.org> From: Bibek Kumar Patro In-Reply-To: <42d627af-164b-4b50-973e-fa71d86cb84c@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 3TCQhyOBUEC9efcom7WpVv2Ar38UDqe8 X-Proofpoint-GUID: 3TCQhyOBUEC9efcom7WpVv2Ar38UDqe8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-12-09_01,2023-12-07_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 mlxscore=0 spamscore=0 priorityscore=1501 suspectscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2312180043 On 12/16/2023 9:45 PM, Dmitry Baryshkov wrote: > On 16/12/2023 02:03, Konrad Dybcio wrote: >> On 15.12.2023 13:54, Robin Murphy wrote: >>> On 2023-12-15 12:20 pm, Bibek Kumar Patro wrote: >>>> >>>> >>>> On 12/15/2023 4:14 PM, Dmitry Baryshkov wrote: >>>>> On Fri, 15 Dec 2023 at 12:19, Bibek Kumar Patro >>>>> wrote: >>>>>> >>>>>> Add ACTLR data table for SM8550 along with support for >>>>>> same including SM8550 specific implementation operations. >>>>>> >>>>>> Signed-off-by: Bibek Kumar Patro >>>>>> --- >>>>>>    drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 89 >>>>>> ++++++++++++++++++++++ >>>>>>    1 file changed, 89 insertions(+) >>>>>> >>>>>> diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >>>>>> b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >>>>>> index cb49291f5233..d2006f610243 100644 >>>>>> --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >>>>>> +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c >>>>>> @@ -20,6 +20,85 @@ struct actlr_config { >>>>>>           u32 actlr; >>>>>>    }; >>>>>> >>>>>> +/* >>>>>> + * SMMU-500 TRM defines BIT(0) as CMTLB (Enable context caching >>>>>> in the >>>>>> + * macro TLB) and BIT(1) as CPRE (Enable context caching in the >>>>>> prefetch >>>>>> + * buffer). The remaining bits are implementation defined and >>>>>> vary across >>>>>> + * SoCs. >>>>>> + */ >>>>>> + >>>>>> +#define PREFETCH_DEFAULT       0 >>>>>> +#define PREFETCH_SHALLOW       BIT(8) >>>>>> +#define PREFETCH_MODERATE      BIT(9) >>>>>> +#define PREFETCH_DEEP          (BIT(9) | BIT(8)) >>>>> >>>>> I thin the following might be more correct: >>>>> >>>>> #include >>>>> >>>>> #define PREFETCH_MASK GENMASK(9, 8) >>>>> #define PREFETCH_DEFAULT FIELD_PREP(PREFETCH_MASK, 0) >>>>> #define PREFETCH_SHALLOW FIELD_PREP(PREFETCH_MASK, 1) >>>>> #define PREFETCH_MODERATE FIELD_PREP(PREFETCH_MASK, 2) >>>>> #define PREFETCH_DEEP FIELD_PREP(PREFETCH_MASK, 3) >>>>> >>>> >>>> Ack, thanks for this suggestion. Let me try this out using >>>> GENMASK. Once tested, will take care of this in next version. >>> >>> FWIW the more typical usage would be to just define the named macros >>> for the raw field values, then put the FIELD_PREP() at the point of >>> use. However in this case that's liable to get pretty verbose, so >>> although I'm usually a fan of bitfield.h, the most readable option >>> here might actually be to stick with simpler definitions of "(0 << >>> 8)", "(1 << 8)", etc. However it's not really a big deal either way, >>> and I defer to whatever Dmitry and Konrad prefer, since they're the >>> ones looking after arm-smmu-qcom the most :) >> My 5 cents would be to just use the "common" style of doing this, so: >> >> #define ACTRL_PREFETCH    GENMASK(9, 8) >>   #define PREFETCH_DEFAULT 0 >>   #define PREFETCH_SHALLOW 1 >>   #define PREFETCH_MODERATE 2 >>   #define PREFETCH_DEEP 3 >> >> and then use >> >> | FIELD_PREP(ACTRL_PREFETCH, PREFETCH_x) >> >> it can get verbose, but.. arguably that's good, since you really want >> to make sure the right bits are set here > > Sounds good to me. > Acked.