From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org
Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org,
mark.rutland@arm.com, james.morse@arm.com,
kvmarm@lists.cs.columbia.edu, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V4 05/17] arm64/cpufeature: Introduce ID_DFR1 CPU register
Date: Tue, 19 May 2020 11:46:32 +0100 [thread overview]
Message-ID: <9d609264-83e4-230e-8d37-46f040b79666@arm.com> (raw)
In-Reply-To: <1589881254-10082-6-git-send-email-anshuman.khandual@arm.com>
On 05/19/2020 10:40 AM, Anshuman Khandual wrote:
> This adds basic building blocks required for ID_DFR1 CPU register which
> provides top level information about the debug system in AArch32 state.
> This is added per ARM DDI 0487F.a specification.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: James Morse <james.morse@arm.com>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
> Cc: kvmarm@lists.cs.columbia.edu
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
>
> Suggested-by: Will Deacon <will@kernel.org>
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 600ce237c487..faf644a66e89 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -457,6 +457,11 @@ static const struct arm64_ftr_bits ftr_id_dfr0[] = {
> ARM64_FTR_END,
> };
>
> +static const struct arm64_ftr_bits ftr_id_dfr1[] = {
> + S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_DFR1_MTPMU_SHIFT, 4, 0),
> + ARM64_FTR_END,
> +};
> +
> diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c
> index cb79b083f97f..50a281703d9d 100644
> --- a/arch/arm64/kernel/cpuinfo.c
> +++ b/arch/arm64/kernel/cpuinfo.c
> @@ -362,6 +362,7 @@ static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info)
> /* Update the 32bit ID registers only if AArch32 is implemented */
> if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
> info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1);
> + info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1);
> info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1);
> info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1);
> info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1);
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index b784b156edb3..0723cfbff7e9 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -1457,7 +1457,7 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> ID_SANITISED(MVFR2_EL1),
> ID_UNALLOCATED(3,3),
> ID_SANITISED(ID_PFR2_EL1),
> - ID_UNALLOCATED(3,5),
> + ID_HIDDEN(ID_DFR1_EL1),
It might be a good idea to mention why this is HIDDEN in the description.
With that :
Reviewed-by : Suzuki K Poulose <suzuki.poulose@arm.com>
next prev parent reply other threads:[~2020-05-19 10:41 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 9:40 [PATCH V4 00/17] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 01/17] arm64/cpufeature: Add explicit ftr_id_isar0[] for ID_ISAR0 register Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 02/17] arm64/cpufeature: Drop TraceFilt feature exposure from ID_DFR0 register Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 03/17] arm64/cpufeature: Make doublelock a signed feature in ID_AA64DFR0 Anshuman Khandual
2020-05-19 10:44 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 04/17] arm64/cpufeature: Introduce ID_PFR2 CPU register Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 05/17] arm64/cpufeature: Introduce ID_DFR1 " Anshuman Khandual
2020-05-19 10:46 ` Suzuki K Poulose [this message]
2020-05-19 9:40 ` [PATCH V4 06/17] arm64/cpufeature: Introduce ID_MMFR5 " Anshuman Khandual
2020-05-19 10:50 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 07/17] arm64/cpufeature: Add remaining feature bits in ID_PFR0 register Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 08/17] arm64/cpufeature: Add remaining feature bits in ID_MMFR4 register Anshuman Khandual
2020-05-19 10:53 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 09/17] arm64/cpufeature: Add remaining feature bits in ID_AA64ISAR0 register Anshuman Khandual
2020-05-19 10:56 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 10/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR0 register Anshuman Khandual
2020-05-19 11:11 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 11/17] arm64/cpufeature: Add remaining feature bits in ID_AA64PFR1 register Anshuman Khandual
2020-05-19 11:13 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 12/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR0 register Anshuman Khandual
2020-05-19 13:32 ` Suzuki K Poulose
2020-05-24 23:08 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 13/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR1 register Anshuman Khandual
2020-05-19 13:44 ` Suzuki K Poulose
2020-05-24 1:09 ` Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 14/17] arm64/cpufeature: Add remaining feature bits in ID_AA64MMFR2 register Anshuman Khandual
2020-05-20 13:56 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 15/17] arm64/cpufeature: Add remaining feature bits in ID_AA64DFR0 register Anshuman Khandual
2020-05-20 13:57 ` Suzuki K Poulose
2020-05-24 1:08 ` Anshuman Khandual
2020-05-25 10:46 ` Suzuki K Poulose
2020-05-19 9:40 ` [PATCH V4 16/17] arm64/cpufeature: Replace all open bits shift encodings with macros Anshuman Khandual
2020-05-19 9:40 ` [PATCH V4 17/17] arm64/cpuinfo: Add ID_MMFR4_EL1 into the cpuinfo_arm64 context Anshuman Khandual
2020-05-20 13:58 ` Suzuki K Poulose
2020-05-21 15:19 ` [PATCH V4 00/17] arm64/cpufeature: Introduce ID_PFR2, ID_DFR1, ID_MMFR5 and other changes Will Deacon
2020-05-25 12:39 ` Anshuman Khandual
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