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Wed, 22 Jan 2025 00:58:05 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 50M0w4Kl016105 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 22 Jan 2025 00:58:04 GMT Received: from [10.110.82.191] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Tue, 21 Jan 2025 16:58:04 -0800 Message-ID: <9d86517e-b05c-4cd6-925e-11c859fcb91d@quicinc.com> Date: Tue, 21 Jan 2025 16:58:03 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 11/35] drm/msm/dpu: get rid of DPU_CTL_ACTIVE_CFG To: Dmitry Baryshkov , Rob Clark , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Vinod Koul , Konrad Dybcio CC: , , , References: <20241214-dpu-drop-features-v1-0-988f0662cb7e@linaro.org> <20241214-dpu-drop-features-v1-11-988f0662cb7e@linaro.org> Content-Language: en-US From: Abhinav Kumar In-Reply-To: <20241214-dpu-drop-features-v1-11-988f0662cb7e@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ezb2_7zdkvTYVUNmVKg1WeN-7K_-qobl X-Proofpoint-GUID: ezb2_7zdkvTYVUNmVKg1WeN-7K_-qobl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-01-21_10,2025-01-21_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 spamscore=0 mlxscore=0 malwarescore=0 mlxlogscore=999 priorityscore=1501 phishscore=0 adultscore=0 suspectscore=0 bulkscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2411120000 definitions=main-2501220005 On 12/13/2024 2:14 PM, Dmitry Baryshkov wrote: > Continue migration to the MDSS-revision based checks and replace > DPU_CTL_ACTIVE_CFG feature bit with the core_major_ver >= 5 check. > > Signed-off-by: Dmitry Baryshkov > --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 8 ++------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h | 8 ++------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_2_sm7150.h | 8 ++------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h | 6 ------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 8 ++------ > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h | 3 --- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 4 ---- > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 2 +- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 7 ++----- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +-- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 - > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 2 +- > 15 files changed, 13 insertions(+), 50 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > index e9bbccc44dad8b391cd51daf902307105b2598fc..e16b0a0c57da4a1aa77064ca2214e37cd9ee4baa 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > @@ -66,7 +66,7 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg( > ctl->ops.setup_intf_cfg(ctl, &intf_cfg); > > /* setup which pp blk will connect to this intf */ > - if (test_bit(DPU_CTL_ACTIVE_CFG, &ctl->caps->features) && phys_enc->hw_intf->ops.bind_pingpong_blk) > + if (phys_enc->hw_intf->ops.bind_pingpong_blk) > phys_enc->hw_intf->ops.bind_pingpong_blk( > phys_enc->hw_intf, > phys_enc->hw_pp->idx); Was it intentional to drop the DPU_CTL_ACTIVE_CFG here but not replace it with core_major_rev >= 5? > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > index 5f9cd09589bb403746d48af6f8555cd224bf3195..59d25916d2d412113768d71a76a6aed4c879299a 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c > @@ -716,7 +716,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *dev, > c->caps = cfg; > c->mdss_ver = mdss_ver; > > - if (c->caps->features & BIT(DPU_CTL_ACTIVE_CFG)) { > + if (mdss_ver->core_major_ver >= 5) { > c->ops.trigger_flush = dpu_hw_ctl_trigger_flush_v1; > c->ops.setup_intf_cfg = dpu_hw_ctl_intf_cfg_v1; > c->ops.reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1; > DPU ver 5 introduced active_cfg, so this part is correct. Hence overall change is fine.