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Thu, 01 Oct 2026 08:17:46 -0700 (PDT) X-Received: by 2002:a05:6102:5ccb:b0:7b4:d43b:43d2 with SMTP id ada2fe7eead31-7be729aee46mr1036346137.3.1790867865602; Thu, 01 Oct 2026 08:17:45 -0700 (PDT) Received: from [192.168.202.12] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6ae5ca73cb0sm1239974a12.26.2026.10.01.08.17.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 01 Oct 2026 08:17:43 -0700 (PDT) Message-ID: <9dc66fa5-47a9-417b-b8ff-b3a61ea75678@oss.qualcomm.com> Date: Thu, 1 Oct 2026 17:17:41 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 1/3] clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width To: Taniya Das , Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Abel Vesa Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Abel Vesa References: <20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com> <20260924-nords_dprx-v2-1-fa4364e087ef@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260924-nords_dprx-v2-1-fa4364e087ef@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: TIi-BWW87LNMomQU3SbfCeP7GE3bu1S2 X-Proofpoint-ORIG-GUID: TIi-BWW87LNMomQU3SbfCeP7GE3bu1S2 X-Authority-Analysis: v=2.4 cv=O8SsLx9W c=1 sm=1 tr=0 ts=6abe799b cx=c_pps a=JIY1xp/sjQ9K5JH4t62bdg==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=EUspDBNiAAAA:8 a=VmrP8RlAhg8Y3bONdaEA:9 a=QEXdDO2ut3YA:10 a=tNoRWFLymzeba-QzToBc:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDAxMDA2MCBTYWx0ZWRfX3XC8L2Okp6kc DPedexzLPFTMcBUdRZ7HTL0Wwi8p8419OWWCw1dEAqms9sOCQWd/2sthclCw0RdipPPGt6PtBPC X54fDRcG50lvjtCK3k7afSPwgMROjDQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDAxMDA2MCBTYWx0ZWRfX6AQStcOT1X+D itX7ZmBUlmgeO4WDVRP08z1r4YxUOfjB/6v7MqcFboQp2eUnPLLcHVB5oLaQQvjQs2cdJOAUemu 5w8oDPif/tLhQDPcQJvhIrW3F8JDgQj/ubQudo9tx+IaQ0FR3svKszHn32eQuVtGUJgC+b+u76q LJOwYMbB/7Dg152Z5viYgzRr1NT1IJfdeWu2qWL9wJjXZvHvAPvRO4zm3iurm0oPpZWIUmID9l7 WioDQZ+3xBSe5FrNdxuYr3jNL+76ak+bDksR5SojqWZwQ5B/BA0tb2A9Ab0Klc0LgzFGstZ30vD d1NyNxaq36VvpZ5ksSFOuuB8mWX2vv+Y7y5z7MMtL1CRM79kW6iFA+UjvQw3ObcnSnmV5UmGr1s tRpk3bdKxNCmM+2y7Ek8cHsG3GhRwtoWQ1+WFxYPwk4msKWxWjWvU3n9JY2mhAbyutiI0cz39TU JV0FtqbZODeOhda0oCw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-01_04,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 bulkscore=0 phishscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610010060 On 9/23/26 9:21 PM, Taniya Das wrote: > On some PLLs the PLL_ALPHA_VAL register has been increased to 28 bits to > carry the fractional word at a finer resolution, for example the > ZONDA_OLE instances on the Qualcomm Nord DPRX. The alpha-PLL core, > however, derives the ALPHA_VAL width solely from the register-map layout > and can only express 16 or 40 bits, so it programs and reads back the > 28-bit configuration at the wrong scale on both the set_rate/slew and > recalc_rate paths, making the PLL lock to and report the wrong rate. > > Add a way to identify the wider register: an optional alpha_width field > in struct clk_alpha_pll that, when non-zero, supersedes the > register-derived width. This feeds pll_alpha_width(), so the recalc_rate > and round_rate math scale the fractional word correctly, and the Zonda > set_rate L-adjust MSB check is derived from the active width instead of > a hardcoded BIT(15). PLLs that leave the field zero retain the previous > behaviour. > > Reviewed-by: Abel Vesa > Signed-off-by: Taniya Das > --- Acked-by: Konrad Dybcio While reviewing this, GPT reports a pre-existing issue, please take a look: zonda_pll_adjust_l_val() in drivers/clk/qcom/clk-alpha-pll.c writes the requested frequency into the PLL's integer divider instead of the calculated quotient. After remainder = do_div(quotient, prate), the assignment should use quotient, but currently reads *l = rate + (u32)(remainder * 2 >= prate). For example, a 1.2 GHz request with a 19.2 MHz parent produces L = 1200000001 instead of 63, which is then written to PLL_L_VAL. This path is taken when the fractional alpha word's MSB is set, so it affects existing Zonda users as well as the proposed 28-bit support. The regression was introduced by a4d89b11aca3 ("clk: qcom: clk-alpha-pll: Simplify the zonda_pll_adjust_l_val()"), which accidentally replaced the quotient with the original rate while simplifying the rounding condition. Replacing rate with quotient in that assignment restores the original calculation without reintroducing the division that caused the ARM32 build failure. Suggested fix: diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -2271,7 +2271,7 @@ static void zonda_pll_adjust_l_val(unsigned long rate, unsigned long prate, u32 *l) quotient = rate; remainder = do_div(quotient, prate); - *l = rate + (u32)(remainder * 2 >= prate); + *l = quotient + (u32)(remainder * 2 >= prate); } Konrad