From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0257B3DA5AF; Wed, 15 Apr 2026 15:24:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.142.180.65 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776266665; cv=none; b=Bpxr7fBX9AoIPCz4+hF/UlzCjbqC1B3/n7WCA1J5unFCEuzTozTV/TeoWVV6eU2tOVqLyMJkegbFAMkCNS1V+Ruqo2jCyeKfploSMLDHzPCAn7oaiRFThSbH7ha3SfepRTiuDdVhgl/BBlKkPdqNuQWxg+Nw+sePbPw2kvTtmUg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1776266665; c=relaxed/simple; bh=Sikh1se6g2anEEvQ5F64ZqS+FzvypM/MKwTerVNjv1Y=; h=Date:From:To:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=lAdkilvrctpp8MnVCcGgNnqNZZ4nFrYoDq90y5IJSv0f+8IieJVZ8glwZpD+vxpmSYMqc3eq4X1TszS063kR9wgiVCjf4+VR/ctUNF68koy/Ug5yy9pT+JZl9wO7MB4iPPO1G6h822SRr0OnQI7LrnqsrXi2jE8d0CncHdAKD44= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org; spf=pass smtp.mailfrom=makrotopia.org; arc=none smtp.client-ip=185.142.180.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=makrotopia.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=makrotopia.org Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.99) (envelope-from ) id 1wD26D-000000002gj-1grm; Wed, 15 Apr 2026 15:24:17 +0000 Date: Wed, 15 Apr 2026 16:24:14 +0100 From: Daniel Golle To: Liam Girdwood , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Jaroslav Kysela , Takashi Iwai , Cyril Chao , Arnd Bergmann , Kuninori Morimoto , Daniel Golle , =?iso-8859-1?Q?N=EDcolas_F=2E_R=2E_A=2E?= Prado , Eugen Hristev , linux-sound@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH 7/9] ARM: dts: mediatek: mt2701: wire HDMI audio path clocks into AFE Message-ID: <9dd80eb5fce5e62e2ce9e006cf5225261b1b984e.1776265610.git.daniel@makrotopia.org> References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Add the HADDS2 PLL 294 MHz root, the audio_hdmi and audio_spdf interface gates and the audio_apll gate to the MT2701 AFE node, and reparent the AUDPLL mux to HADDS2PLL_98M so the HDMI audio serial clock path has a stable 294.912 MHz source. The clock names match the updated mediatek,mt2701-audio binding. Signed-off-by: Daniel Golle --- arch/arm/boot/dts/mediatek/mt2701.dtsi | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/arm/boot/dts/mediatek/mt2701.dtsi b/arch/arm/boot/dts/mediatek/mt2701.dtsi index 128b87229f3d5..80c8c7e6a422a 100644 --- a/arch/arm/boot/dts/mediatek/mt2701.dtsi +++ b/arch/arm/boot/dts/mediatek/mt2701.dtsi @@ -464,7 +464,11 @@ afe: audio-controller { <&audsys CLK_AUD_AFE_CONN>, <&audsys CLK_AUD_A1SYS>, <&audsys CLK_AUD_A2SYS>, - <&audsys CLK_AUD_AFE_MRGIF>; + <&audsys CLK_AUD_AFE_MRGIF>, + <&topckgen CLK_TOP_HADDS2PLL_294M>, + <&audsys CLK_AUD_HDMI>, + <&audsys CLK_AUD_SPDF>, + <&audsys CLK_AUD_APLL>; clock-names = "infra_sys_audio_clk", "top_audio_mux1_sel", @@ -499,15 +503,22 @@ afe: audio-controller { "audio_afe_conn_pd", "audio_a1sys_pd", "audio_a2sys_pd", - "audio_mrgif_pd"; + "audio_mrgif_pd", + "hadds2pll_294m", + "audio_hdmi_pd", + "audio_spdf_pd", + "audio_apll_pd"; assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, <&topckgen CLK_TOP_AUD_MUX2_SEL>, <&topckgen CLK_TOP_AUD_MUX1_DIV>, - <&topckgen CLK_TOP_AUD_MUX2_DIV>; + <&topckgen CLK_TOP_AUD_MUX2_DIV>, + <&topckgen CLK_TOP_AUDPLL_MUX_SEL>; assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, - <&topckgen CLK_TOP_AUD2PLL_90M>; - assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; + <&topckgen CLK_TOP_AUD2PLL_90M>, + <0>, <0>, + <&topckgen CLK_TOP_HADDS2PLL_98M>; + assigned-clock-rates = <0>, <0>, <49152000>, <45158400>, <0>; }; }; -- 2.53.0