From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932926AbdEOIT7 (ORCPT ); Mon, 15 May 2017 04:19:59 -0400 Received: from bastet.se.axis.com ([195.60.68.11]:58797 "EHLO bastet.se.axis.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1760110AbdEOIT3 (ORCPT ); Mon, 15 May 2017 04:19:29 -0400 Subject: Re: [PATCH 1/3] arm64: dts: hi3660: add pcie node To: Song Xiaowei , , , , , , , , CC: , , , , , References: <20170515062745.70082-1-songxiaowei@hisilicon.com> From: Niklas Cassel Message-ID: <9e2ed522-d808-8984-cc5a-316c392363d5@axis.com> Date: Mon, 15 May 2017 10:19:18 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.0.1 MIME-Version: 1.0 In-Reply-To: <20170515062745.70082-1-songxiaowei@hisilicon.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.0.5.60] X-ClientProxiedBy: XBOX04.axis.com (10.0.5.18) To XBOX02.axis.com (10.0.5.16) X-TM-AS-GCONF: 00 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hello Song You forgot to add the device tree maintainers and the device tree mailing list to this patch. If you use ./scripts/get_maintainer.pl it will show you this information. Regards, Niklas On 05/15/2017 08:27 AM, Song Xiaowei wrote: > Add PCIe node for hi3660, and add binding documentation. > > Cc: Guodong Xu > Signed-off-by: Song Xiaowei > --- > .../devicetree/bindings/pci/hisilicon-pcie.txt | 52 ++++++++++++++++++++++ > arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++ > 2 files changed, 83 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt > index a339dbb15493..71491178c86c 100644 > --- a/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt > +++ b/Documentation/devicetree/bindings/pci/hisilicon-pcie.txt > @@ -85,3 +85,55 @@ Example: > 0x0 0 0 4 &mbigen_pcie0 650 4>; > status = "ok"; > }; > + > + > + > +HiSilicon Kirin SoC PCIe host DT description > + > +Kirin PCIe host controller is also based on Designware PCI core. > +It shares common functions with PCIe Designware core driver and inherits > +common properties defined in > +Documentation/devicetree/bindings/pci/designware-pci.txt. > + > +Additional properties are described here: > + > +Required properties > +- compatible: Should contain "hisilicon,kirin-pcie". > +- reg: Should contain rc_dbi, apb, phy, config registers location and length. > +- reg-names: Must include the following entries: > + "dbi": controller configuration registers; > + "apb": apb Ctrl register; > + "phy": apb PHY register; > + "config": PCIe configuration space registers. > +- reset-gpio: perst assert/deassert gpio > + > +Optional properties: > +- status: Either "ok" or "disabled". > + > +Kirin960 Example: > + kirin_pcie@f4000000 { > + compatible = "hisilicon,kirin-pcie"; > + reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>, > + <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF5000000 0 0x2000>; > + reg-names = "dbi","apb","phy", "config"; > + bus-range = <0x0 0x1>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x02000000 0x0 0x00000000 0x0 0xf6000000 0x0 0x2000000>; > + num-lanes = <1>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0xf800 0 0 7>; > + interrupt-map = <0x0 0 0 2 &gic 0 0 0 283 4>, > + <0x0 0 0 3 &gic 0 0 0 284 4>, > + <0x0 0 0 4 &gic 0 0 0 285 4>; > + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, > + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, > + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; > + clock-names = "pcie_phy_ref", "pcie_aux", > + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; > + reset-gpio = <&gpio11 1 0 >; > + status = "ok"; > + }; > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > index 3983086bd67b..2406a54947df 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > @@ -156,5 +156,36 @@ > clock-names = "uartclk", "apb_pclk"; > status = "disabled"; > }; > + > + kirin_pcie@f4000000 { > + compatible = "hisilicon,kirin-pcie"; > + reg = <0x0 0xf4000000 0x0 0x1000>, > + <0x0 0xff3fe000 0x0 0x1000>, > + <0x0 0xf3f20000 0x0 0x40000>, > + <0x0 0xF5000000 0x0 0x2000>; > + reg-names = "dbi", "apb", "phy", "config"; > + bus-range = <0x0 0x1>; > + #address-cells = <3>; > + #size-cells = <2>; > + device_type = "pci"; > + ranges = <0x02000000 0x0 0x00000000 0x0 > + 0xf6000000 0x0 0x2000000>; > + num-lanes = <1>; > + #interrupt-cells = <1>; > + interrupt-map-mask = <0xf800 0 0 7>; > + interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>, > + <0x0 0 0 2 &gic 0 0 0 283 4>, > + <0x0 0 0 3 &gic 0 0 0 284 4>, > + <0x0 0 0 4 &gic 0 0 0 285 4>; > + clocks = <&crg_ctrl HI3660_PCIEPHY_REF>, > + <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>, > + <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>, > + <&crg_ctrl HI3660_ACLK_GATE_PCIE>; > + clock-names = "pcie_phy_ref", "pcie_aux", > + "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk"; > + reset-gpio = <&gpio11 1 0 >; > + status = "ok"; > + }; > }; > }; >