From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D2732269B1C for ; Wed, 27 May 2026 05:52:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779861148; cv=none; b=DsKIW+5h3auFukOmgr07XosUKSjrF5IBqzthJZxd50AOzhQbLjX7LdcAy9rRZkA/ImfR9pZxZbOdmOhWQhxxkbZzI3G/vfJ05iSHRmLFH2W9//EJ/CUiDItx+cdnyF886KLbO1ZIEGcopTdS3WllU9BhdI+bcJ0bLzeJrKqg0Fo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779861148; c=relaxed/simple; bh=kN7v8Yo/h9jLVzSWJYwp5pXMcuNhkzPz7FVEiIHcY5E=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=VP5TEdbvBWbpaRg2m87qlsHcYWktZBGHdr1hXLBc60dJSZ/Ch4nS2I6hUeS1z+7XwoUHlOapCHEFqxHWbFvBbi9G+qAtpda5lOmSNzQqCQgGSi3fEvoA6F9+IoLXwlPfxTh/WM7uVOmGgobzZ4bq/nHL8z53A1HcAsuzeKLlIU0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b=mAxCWDZs; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=arm.com header.i=@arm.com header.b="mAxCWDZs" Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 1EA7A16F2; Tue, 26 May 2026 22:43:12 -0700 (PDT) Received: from [10.164.19.7] (unknown [10.164.19.7]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 22BAA3F632; Tue, 26 May 2026 22:43:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1779860597; bh=kN7v8Yo/h9jLVzSWJYwp5pXMcuNhkzPz7FVEiIHcY5E=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=mAxCWDZsUUqwMXDxAEIrGKbX+vEH2ZtBW3H5sftYz90tkf+jWEvMRM58EXGsOd5OH /4JoDFW3EvPipQtTEXBdiPAAkNZQh16kAU2D2kd2ukurqyQmjmDJGTzVRiTh1sjbeU PCPEY+mYQKZo353Hglks4w84JtcVfQdZb2/VSHqU= Message-ID: <9e3343c3-eef3-419b-868d-ab02dc66e47d@arm.com> Date: Wed, 27 May 2026 11:13:08 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 2/6] arm64/vmalloc: Allow arch_vmap_pte_range_map_size to batch multiple CONT_PTE To: Wen Jiang , linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, akpm@linux-foundation.org, urezki@gmail.com Cc: baohua@kernel.org, Xueyuan.chen21@gmail.com, rppt@kernel.org, david@kernel.org, ryan.roberts@arm.com, anshuman.khandual@arm.com, ajd@linux.ibm.com, linux-kernel@vger.kernel.org, jiangwen6@xiaomi.com References: <20260522053146.83209-1-jiangwenxiaomi@gmail.com> <20260522053146.83209-3-jiangwenxiaomi@gmail.com> Content-Language: en-US From: Dev Jain In-Reply-To: <20260522053146.83209-3-jiangwenxiaomi@gmail.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 22/05/26 11:01 am, Wen Jiang wrote: > From: "Barry Song (Xiaomi)" > > Allow arch_vmap_pte_range_map_size to batch multiple CONT_PTE hugepages, ..."to batch across multiple CONT_PTE blocks" > reducing both PTE setup and TLB flush iterations. > > Signed-off-by: Barry Song (Xiaomi) > Signed-off-by: Wen Jiang > Tested-by: Xueyuan Chen > --- > arch/arm64/include/asm/vmalloc.h | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/vmalloc.h b/arch/arm64/include/asm/vmalloc.h > index 4ec1acd3c1b34..787fd17b48e2c 100644 > --- a/arch/arm64/include/asm/vmalloc.h > +++ b/arch/arm64/include/asm/vmalloc.h > @@ -23,6 +23,8 @@ static inline unsigned long arch_vmap_pte_range_map_size(unsigned long addr, > unsigned long end, u64 pfn, > unsigned int max_page_shift) > { > + unsigned long size; > + > /* > * If the block is at least CONT_PTE_SIZE in size, and is naturally > * aligned in both virtual and physical space, then we can pte-map the > @@ -40,7 +42,9 @@ static inline unsigned long arch_vmap_pte_range_map_size(unsigned long addr, > if (!IS_ALIGNED(PFN_PHYS(pfn), CONT_PTE_SIZE)) > return PAGE_SIZE; > > - return CONT_PTE_SIZE; > + size = min3(end - addr, 1UL << max_page_shift, PMD_SIZE >> 1); > + size = 1UL << __fls(size); > + return size; > } > > #define arch_vmap_pte_range_unmap_size arch_vmap_pte_range_unmap_size