From: Paul Walmsley <pjw@kernel.org>
To: Yong-Xuan Wang <yongxuan.wang@sifive.com>
Cc: Anup Patel <anup@brainfault.org>,
Atish Patra <atish.patra@linux.dev>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
greentime.hu@sifive.com, vincent.chen@sifive.com,
zong.li@sifive.com, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org,
Samuel Holland <samuel.holland@sifive.com>
Subject: Re: [PATCH v2] RISC-V: Clear HSTATUS.HU on CPU initialization
Date: Wed, 30 Sep 2026 21:02:16 -0600 (MDT) [thread overview]
Message-ID: <9e3dd333-2747-45dd-6880-2b83a3778f66@kernel.org> (raw)
In-Reply-To: <20260924-hstatus_hu-v2-1-7e970f5f1d8d@sifive.com>
On Thu, 24 Sep 2026, Yong-Xuan Wang wrote:
> The RISC-V privileged specification does not mandate HSTATUS reset
> values, leaving the HU bit potentially set after hardware reset.
> When HU=1, hypervisor instructions (HLV/HLVX/HSV) can execute in
> U-mode to access guest memory, which may cause unintended behavior
> if not explicitly controlled.
>
> Clear HSTATUS.HU during CPU initialization to ensure hypervisor
> instructions are only available in HS-mode, preventing unexpected
> guest memory access from U-mode code.
>
> Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Thanks, queued for v7.3-rc.
- Paul
prev parent reply other threads:[~2026-10-01 3:02 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-24 10:16 Yong-Xuan Wang
2026-10-01 3:02 ` Paul Walmsley [this message]
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