From: Claudiu Beznea <claudiu.beznea@tuxon.dev>
To: ALOK TIWARI <alok.a.tiwari@oracle.com>,
bhelgaas@google.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be,
magnus.damm@gmail.com, p.zabel@pengutronix.de
Cc: linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>,
Wolfram Sang <wsa+renesas@sang-engineering.com>
Subject: Re: [External] : [PATCH v7 2/6] PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver
Date: Wed, 19 Nov 2025 14:37:09 +0200 [thread overview]
Message-ID: <9e459cff-7e6c-409e-ac34-9978fb501e51@tuxon.dev> (raw)
In-Reply-To: <32bec7e0-6631-4850-835b-c0c377722dca@oracle.com>
Hi, Alok,
On 11/17/25 16:04, ALOK TIWARI wrote:
>> +
>> +/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
>> +static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn,
>> + int where, int size, u32 val)
>> +{
>> + struct rzg3s_pcie_host *host = bus->sysdata;
>> +
>> + /* Enable access control to the CFGU */
>> + writel_relaxed(RZG3S_PCI_PERM_CFG_HWINIT_EN,
>> + host->axi + RZG3S_PCI_PERM);
>> +
>> + pci_generic_config_write(bus, devfn, where, size, val);
>
> why ignore pci_generic_config_write ret ?
Missed it.
>
>> +
>> + /* Disable access control to the CFGU */
>> + writel_relaxed(0, host->axi + RZG3S_PCI_PERM);
>> +
>> + return PCIBIOS_SUCCESSFUL;
>> +}
[...]
>> +static int rzg3s_pcie_init_msi(struct rzg3s_pcie_host *host)
>> +{
>> + struct platform_device *pdev = to_platform_device(host->dev);
>> + struct rzg3s_pcie_msi *msi = &host->msi;
>> + struct device *dev = host->dev;
>> + const char *devname;
>> + int irq, ret;
>> +
>> + ret = devm_mutex_init(dev, &msi->map_lock);
>> + if (ret)
>> + return ret;
>> +
>> + msi->irq = platform_get_irq_byname(pdev, "msi");
>> + if (msi->irq < 0)
>> + return dev_err_probe(dev, irq ? irq : -EINVAL,
>> + "Failed to get MSI IRQ!\n");
>
> irq is uninitialized. do you mean msi->irq?
Good catch, I'll update it.
>
>> +
>> + devname = devm_kasprintf(dev, GFP_KERNEL, "%s-msi", dev_name(dev));
>> + if (!devname)
>> + return -ENOMEM;
>> +
>> + ret = rzg3s_pcie_msi_allocate_domains(msi);
>> + if (ret)
>> + return ret;
>> +
>> + /*
>> + * Don't use devm_request_irq() as the driver uses non-devm helpers
>> + * to control clocks. Mixing them may lead to subtle bugs.
>> + */
>> + ret = request_irq(msi->irq, rzg3s_pcie_msi_irq, 0, devname, host);
>> + if (ret) {
>> + dev_err_probe(dev, ret, "Failed to request IRQ: %d\n", ret);
>> + goto free_domains;
>> + }
>> +
>> + ret = rzg3s_pcie_msi_setup(host);
>> + if (ret) {
>> + dev_err_probe(dev, ret, "Failed to setup MSI!\n");
>> + goto free_irq;
>> + }
>> +
>> + return 0;
>> +
>> +free_irq:
>> + free_irq(msi->irq, host);
>> +free_domains:
>> + irq_domain_remove(msi->domain);
>> + return ret;
>> +}
>> +
>> +static void rzg3s_pcie_intx_irq_ack(struct irq_data *d)
>> +{
>> + struct rzg3s_pcie_host *host = irq_data_get_irq_chip_data(d);
>> +
>> + guard(raw_spinlock_irqsave)(&host->hw_lock);
>> +
>> + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS,
>> + RZG3S_PCI_PINTRCVIS_INTX(d->hwirq),
>> + RZG3S_PCI_PINTRCVIS_INTX(d->hwirq));
>> +}
>> +
>> +static int
>> +rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host,
>> + int (*init_irqdomain)(struct rzg3s_pcie_host *host),
>> + void (*teardown_irqdomain)(struct rzg3s_pcie_host *host))
>> +{
>> + struct device *dev = host->dev;
>> + int ret;
>> +
>> + /* Set inbound windows */
>> + ret = rzg3s_pcie_parse_map_dma_ranges(host);
>> + if (ret)
>> + return dev_err_probe(dev, ret,
>> + "Failed to set inbound windows!\n");
>> +
>> + /* Set outbound windows */
>> + ret = rzg3s_pcie_parse_map_ranges(host);
>> + if (ret)
>> + return dev_err_probe(dev, ret,
>> + "Failed to set outbound windows!\n");
>> +
>> + ret = init_irqdomain(host);
>> + if (ret)
>> + return dev_err_probe(dev, ret, "Failed to init IRQ doamin\n");
>
> typo doamin -> domain
Same here.
Thank you for your review,
Claudiu
next prev parent reply other threads:[~2025-11-19 12:37 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-17 9:08 [PATCH v7 0/6] PCI: rzg3s-host: Add PCIe driver for Renesas RZ/G3S SoC Claudiu
2025-11-17 9:08 ` [PATCH v7 1/6] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add Renesas RZ/G3S Claudiu
2025-11-17 9:08 ` [PATCH v7 2/6] PCI: rzg3s-host: Add Renesas RZ/G3S SoC host driver Claudiu
2025-11-17 14:04 ` [External] : " ALOK TIWARI
2025-11-19 12:37 ` Claudiu Beznea [this message]
2025-11-17 9:08 ` [PATCH v7 3/6] arm64: dts: renesas: r9a08g045: Add PCIe node Claudiu
2025-11-17 9:08 ` [PATCH v7 4/6] arm64: dts: renesas: rzg3s-smarc-som: Add PCIe reference clock Claudiu
2025-11-17 9:08 ` [PATCH v7 5/6] arm64: dts: renesas: rzg3s-smarc: Enable PCIe Claudiu
2025-11-17 9:08 ` [PATCH v7 6/6] arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC Claudiu
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