From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 238283B102B for ; Tue, 12 May 2026 14:26:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595991; cv=none; b=XkBwOTmkqX1+Ip89bIODZvfV2ZJgBB0FOjedvmFnMoJsKJ9AVpn25vb7d3LD0NPO+MmCDDgyVBX5mR5vF/jHiIMLieHzCzg4bI6ln6KbTtX9o9SXKvYFseL+8JZsMVAvCCMk7GvveUmdpqTQ1o5lkRSqMpvc+9d/6Eti1B4PXPU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778595991; c=relaxed/simple; bh=h+3qov3k+VwgkdZvrPuDzMAklnb5ZHuO2HBKmVLnsjg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=IXk+bOmHBZUOrO5Pq6Mmc+lUzCfwNznpoINQ4LgUdUoU52zi0dHLka9L+vhMHJM/mSUlBlPRAN/Df+cZol0aQgm265bPz5UtSSSfdobebZXAOloHegFYNdVeURgf11TU0BzEwN7ue5A4YMsk1jy88/y0bFzKCi9N46Rf1l7gWHc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=B4JyUvE9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="B4JyUvE9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 628C6C2BCB0; Tue, 12 May 2026 14:26:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778595990; bh=h+3qov3k+VwgkdZvrPuDzMAklnb5ZHuO2HBKmVLnsjg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=B4JyUvE9HtW+dVH53U19iwP4XVJ0D/TlJKzCPAQ8h1bOj83JrtiZQyfhJqCZJbQNL j4UI78vhv1hcZI8r43ZtkzAgUazJ3JbnmjoCEyE4u0aEZIKu/DkNpeVALcCtELvAeD r14U5B5Lnr/6XfjaVH8z19y0AryhJQLBt/7HC5emcZ6KGwalJNRqzpca0ubDLNS9WK 88JXSjYAms4HVXmEJruTiYS8iyNbmo5BCoW2r4MyX5neE1F04F50V5U2+qynkwkECV 8xaTVR4/F8jj+V8XLD4vbl8KPn18Vq9XsDJEhnyS6RZvp/Ay3Ib1UiRHc9OG5QyJlA xJWprhJRpk+8w== From: "Naveen N Rao (AMD)" To: Cc: Thomas Gleixner , Borislav Petkov , Dave Hansen , "H. Peter Anvin" , Nikunj A Dadhania , Manali Shukla , Bharata B Rao , Subject: [PATCH v2 1/3] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10 Date: Tue, 12 May 2026 19:49:15 +0530 Message-ID: <9e5fb0818b73e4ac72e2137b1cff90685a3ad528.1778594390.git.naveen@kernel.org> X-Mailer: git-send-email 2.54.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit For AMD family 0x10, EILVT offsets are not assigned by BIOS and is instead assigned by picking the next available EILVT offset. Use the maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than an arbitrary maximum EILVT count when looking for the next available EILVT offset. Signed-off-by: Naveen N Rao (AMD) Tested-by: Manali Shukla --- arch/x86/events/amd/ibs.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 20c2de5c697b..ad73a002f8cd 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1839,13 +1839,13 @@ static void force_ibs_eilvt_setup(void) preempt_disable(); /* find the next free available EILVT entry, skip offset 0 */ - for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) { + for (offset = 1; offset < APIC_EILVT_NR_AMD_10H; offset++) { if (get_eilvt(offset)) break; } preempt_enable(); - if (offset == APIC_EILVT_NR_MAX) { + if (offset == APIC_EILVT_NR_AMD_10H) { pr_debug("No EILVT entry available\n"); return; } -- 2.54.0