From: "Aiqun(Maria) Yu" <quic_aiquny@quicinc.com>
To: Marc Zyngier <maz@kernel.org>
Cc: <will@kernel.org>, <corbet@lwn.net>, <catalin.marinas@arm.com>,
<quic_pkondeti@quicinc.com>, <quic_kaushalk@quicinc.com>,
<quic_satyap@quicinc.com>, <quic_shashim@quicinc.com>,
<quic_songxue@quicinc.com>, <linux-doc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] arm64: Add the arm64.nolse_atomics command line option
Date: Wed, 12 Jul 2023 10:47:55 +0800 [thread overview]
Message-ID: <9e69158f-1e67-344b-fea9-85bb5e21183f@quicinc.com> (raw)
In-Reply-To: <86cz0ywx5p.wl-maz@kernel.org>
On 7/11/2023 6:38 PM, Marc Zyngier wrote:
> On Tue, 11 Jul 2023 11:12:48 +0100,
> "Aiqun(Maria) Yu" <quic_aiquny@quicinc.com> wrote:
>>
>> For the KVM part, per my understanding, as long as the current feature
>> id being overriden, the KVM system also get the current vcpu without
>> the lse atomic feature enabled.
>> KVM vcpu will read the sys reg from host arm64_ftr_regs which is
>> already been controled by the idreg_overrides.
>
> You're completely missing the point.
>
> The guest is free to map memory as non-cacheable *and* to use LSE
> atomics even if the idregs pretend this is not available. At which
The guest also can have the current linux kernel mechanism of LSE ATOMIC
way.
+----------------------------+
| |
| Read the cpu feature IDs |
+----------------------------+
v
+----------------------------+ +-------------------+
| | Y | Use lse atomic ins|
| if lse atomic supported | -- | |
+----------------------------+ +-------------------+
v N
+----------------------------+
| Use r/stxr + atomic ins |
| |
+----------------------------+
Just like other KVM vcpu cpu features, lse atomic can be a feature
inherit from the pysical cpu features for the KVM vcpus.
> point the HW throws a fit and the system is dead. Is that acceptable?
> Of course not.
>
The current patchset is try to have the ability to *kind of free* to not
make system dead. Since currently linux kernel already have the runtime
patching of lse atomic ops, we are trying to have user have option to
re-use the switch of system_uses_lse_atomics().
#define __lse_ll_sc_body(op, ...) \
({ \
system_uses_lse_atomics() ? \
__lse_##op(__VA_ARGS__) : \
__ll_sc_##op(__VA_ARGS__); \
})
> So there are two aspects to your problem:
>
> - for Linux, there is nothing to do: the kernel will correctly behave,
> and as long as you don't expose non-cacheable memory to userspace.
> Out of tree drivers are none of our concern here.
>
For Linux kernel, we have provide the In-line patching at runtime, and
all third party kernel modules are built with those in-line patching as
well.
if we can have an option, the current system can still run those third
party kernel modules without system crash.
/* In-line patching at runtime */
#define ARM64_LSE_ATOMIC_INSN(llsc, lse) \
ALTERNATIVE(llsc, __LSE_PREAMBLE lse, ARM64_HAS_LSE_ATOMICS)
static __always_inline bool system_uses_lse_atomics(void)
{
return alternative_has_cap_likely(ARM64_HAS_LSE_ATOMICS);
}
> - for guests, it looks like the HW doesn't provide the basic
> requirements for virtualisation, and you should always disable KVM
> on this HW (or even better, enter the kernel at EL1).
>
I can see that KVM can still be supported even if current phisical cpu
don't have emulated vcpu features. We can only disable the current vcpu
feature which exposed to KVM guest.
> In both cases, nothing to do in the kernel, which is good news.
>
> M.
>
--
Thx and BRs,
Aiqun(Maria) Yu
next prev parent reply other threads:[~2023-07-12 2:48 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-10 5:59 Maria Yu
2023-07-10 6:07 ` Randy Dunlap
2023-07-10 6:13 ` Aiqun(Maria) Yu
2023-07-10 7:27 ` Marc Zyngier
2023-07-10 8:19 ` Aiqun(Maria) Yu
2023-07-10 9:31 ` Marc Zyngier
2023-07-11 3:30 ` Aiqun(Maria) Yu
2023-07-11 6:57 ` Marc Zyngier
2023-07-11 10:12 ` Aiqun(Maria) Yu
2023-07-11 10:38 ` Marc Zyngier
2023-07-12 2:47 ` Aiqun(Maria) Yu [this message]
2023-07-12 7:29 ` Marc Zyngier
2023-07-12 8:03 ` Aiqun(Maria) Yu
2023-07-10 9:37 ` Will Deacon
2023-07-11 4:02 ` Aiqun(Maria) Yu
2023-07-11 8:22 ` Will Deacon
2023-07-11 10:15 ` Aiqun(Maria) Yu
2023-07-11 10:25 ` Will Deacon
2023-07-12 3:09 ` Aiqun(Maria) Yu
2023-07-12 7:36 ` Mark Rutland
2023-07-13 2:24 ` Aiqun(Maria) Yu
2023-07-13 11:20 ` Mark Rutland
2023-07-13 14:08 ` Aiqun(Maria) Yu
2023-07-13 19:08 ` Mark Rutland
2023-07-14 1:56 ` Aiqun(Maria) Yu
2023-07-14 8:23 ` Will Deacon
2023-07-14 10:12 ` Aiqun(Maria) Yu
2023-07-14 12:09 ` Will Deacon
2023-07-17 2:01 ` Aiqun(Maria) Yu
2023-07-11 10:34 ` Mark Rutland
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