Re: [PATCH v2 2/2] arm64: dts: socfpga: agilex: add Agilex SoCDK multi-QSPI board

["Chan, Genevieve" <genevieve.chan@altera.com>]

Hi Dinh,
Apologies, v3 only addressed one of your three comments on v2. I
missed the other two; replies are inline below, and both are fixed in
v4.

On 7/10/2026 9:43 pm, Dinh Nguyen wrote:
> 
> NIT: your commit header "arm64: dts: socfpga: agilex: add Agilex SoCDK
> multi-QSPI board"
> 
> Avoid using the same name multiple times. Please reword this to
> 
> arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board
> 
> or
> 
> arm64: dts: socfpga: add Agilex SoCDK multi-QSPI board
> 

Done in v3, using the first form.
> 
> On 10/5/26 21:54, genevieve.chan@altera.com wrote:
>> From: Genevieve Chan <genevieve.chan@altera.com>
>>
>> Add a device tree for the Agilex SoCDK fitted with the multi-QSPI
>> daughter board. The daughter board replaces the single QSPI flash of
>> the default SoCDK with four Micron MT25QU02G flashes on chip selects
>> 0-3, which allows the system to use up to 1 GiB of QSPI storage.
>>
>> The board is otherwise identical to the SoCDK and builds on
>> socfpga_agilex.dtsi.
>>
>> Signed-off-by: Genevieve Chan <genevieve.chan@altera.com>
>> ---
>> Changes in v2:
>> - Rename file, compatible and model to drop the "agilex7f" prefix.
>> - Reword commit message to describe the hardware.
>>
>>   arch/arm64/boot/dts/intel/Makefile            |   1 +
>>   .../intel/socfpga_agilex_socdk_multiqspi.dts  | 213 ++++++++++++++++++
>>   2 files changed, 214 insertions(+)
>>   create mode 100644 arch/arm64/boot/dts/intel/
>> socfpga_agilex_socdk_multiqspi.dts
>>
>> diff --git a/arch/arm64/boot/dts/intel/Makefile b/arch/arm64/boot/dts/
>> intel/Makefile
>> index b52cd2330cef..071bad408688 100644
>> --- a/arch/arm64/boot/dts/intel/Makefile
>> +++ b/arch/arm64/boot/dts/intel/Makefile
>> @@ -2,6 +2,7 @@
>>   dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
>>                   socfpga_agilex_socdk.dtb \
>>                   socfpga_agilex_socdk_emmc.dtb \
>> +                socfpga_agilex_socdk_multiqspi.dtb \
>>                   socfpga_agilex_socdk_nand.dtb \
>>                   socfpga_agilex3_socdk.dtb \
>>                   socfpga_agilex5_socdk.dtb \
>> diff --git a/arch/arm64/boot/dts/intel/
>> socfpga_agilex_socdk_multiqspi.dts b/arch/arm64/boot/dts/intel/
>> socfpga_agilex_socdk_multiqspi.dts
>> new file mode 100644
>> index 000000000000..0bf087fa7553
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk_multiqspi.dts
>> @@ -0,0 +1,213 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * Copyright (C) 2026, Intel Corporation
>> + */
>> +#include "socfpga_agilex.dtsi"
>> +
>> +/ {
>> +    model = "SoCFPGA Agilex SoCDK multi-QSPI daughter board";
>> +    compatible = "intel,socfpga-agilex-socdk-multiqspi",
>> "intel,socfpga-agilex";
>> +
>> +    aliases {
>> +        serial0 = &uart0;
>> +        ethernet0 = &gmac0;
>> +        ethernet1 = &gmac1;
>> +        ethernet2 = &gmac2;
>> +    };
>> +
>> +    chosen {
>> +        stdout-path = "serial0:115200n8";
>> +    };
>> +
>> +    leds {
>> +        compatible = "gpio-leds";
>> +        led0 {
>> +            label = "hps_led0";
>> +            gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
>> +        };
>> +
>> +        led1 {
>> +            label = "hps_led1";
>> +            gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
>> +        };
>> +
>> +        led2 {
>> +            label = "hps_led2";
>> +            gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
>> +        };
>> +    };
>> +
>> +    memory@80000000 {
>> +        device_type = "memory";
>> +        /* We expect the bootloader to fill in the reg */
>> +        reg = <0 0x80000000 0 0>;
>> +    };
>> +};
>> +
>> +&gpio1 {
>> +    status = "okay";
>> +};
>> +
>> +&gmac0 {
>> +    status = "okay";
>> +    /* PHY delays are configured via skew properties */
>> +    phy-mode = "rgmii";
>> +    phy-handle = <&phy0>;
>> +
>> +    max-frame-size = <9000>;
>> +
>> +    mdio0 {
>> +        #address-cells = <1>;
>> +        #size-cells = <0>;
>> +        compatible = "snps,dwmac-mdio";
>> +        phy0: ethernet-phy@4 {
>> +            reg = <4>;
>> +
>> +            txd0-skew-ps = <0>; /* -420ps */
>> +            txd1-skew-ps = <0>; /* -420ps */
>> +            txd2-skew-ps = <0>; /* -420ps */
>> +            txd3-skew-ps = <0>; /* -420ps */
>> +            rxd0-skew-ps = <420>; /* 0ps */
>> +            rxd1-skew-ps = <420>; /* 0ps */
>> +            rxd2-skew-ps = <420>; /* 0ps */
>> +            rxd3-skew-ps = <420>; /* 0ps */
>> +            txen-skew-ps = <0>; /* -420ps */
>> +            txc-skew-ps = <900>; /* 0ps */
>> +            rxdv-skew-ps = <420>; /* 0ps */
>> +            rxc-skew-ps = <1680>; /* 780ps */
>> +        };
>> +    };
>> +};
>> +
>> +&mmc {
>> +    status = "okay";
>> +    cap-sd-highspeed;
>> +    broken-cd;
>> +    bus-width = <4>;
>> +    clk-phase-sd-hs = <0>, <135>;
>> +};
>> +
>> +&osc1 {
>> +    clock-frequency = <25000000>;
>> +};
>> +
>> +&uart0 {
>> +    status = "okay";
>> +};
>> +
>> +&usb0 {
>> +    status = "okay";
>> +    disable-over-current;
>> +};
>> +
>> +&watchdog0 {
>> +    status = "okay";
>> +};
>> +
>> +&qspi {
>> +    status = "okay";
>> +
>> +    flash@0 {
>> +        compatible = "micron,mt25qu02g", "jedec,spi-nor";
>> +        reg = <0>;
>> +        spi-max-frequency = <25000000>;
> 
> The devkit has 100 MHz, why is this card only 25M MHz?
Yes, the SoCDK runs its QSPI flash at 100 MHz. The default SoCDK QSPI
card has a single flash on the bus. On the multi-QSPI card, the four
MT25QU02G devices share SCLK and DQ[3:0], with only the chip selects
routed separately. The added load of four devices, plus the longer
routing on the daughter card, lowers the clock the bus can run reliably.
Altera's multi-QSPI reference design for this card is validated at 25
MHz, so the DTS uses that value.

I'll add this to the commit message in v4.
>> +
>> +        m25p,fast-read;
>> +        cdns,read-delay = <2>;
>> +        cdns,tshsl-ns = <50>;
>> +        cdns,tsd2d-ns = <50>;
>> +        cdns,tchsh-ns = <4>;
>> +        cdns,tslch-ns = <4>;
>> +        spi-tx-bus-width = <4>;
>> +        spi-rx-bus-width = <4>;
>> +
>> +        partitions {
>> +            compatible = "fixed-partitions";
>> +            #address-cells = <1>;
>> +            #size-cells = <1>;
>> +
>> +            qspi_boot0: partition@0 {
>> +                label = "Boot and fpga data";
>> +                reg = <0x0 0x10000000>;
>> +            };
>> +        };
>> +    };
>> +
>> +    flash@1 {
>> +        compatible = "micron,mt25qu02g", "jedec,spi-nor";
>> +        reg = <1>;
>> +        spi-max-frequency = <25000000>;
>> +
>> +        m25p,fast-read;
>> +        cdns,read-delay = <2>;
>> +        cdns,tshsl-ns = <50>;
>> +        cdns,tsd2d-ns = <50>;
>> +        cdns,tchsh-ns = <4>;
>> +        cdns,tslch-ns = <4>;
>> +        spi-tx-bus-width = <4>;
>> +        spi-rx-bus-width = <4>;
>> +
>> +        partitions {
>> +            compatible = "fixed-partitions";
>> +            #address-cells = <1>;
>> +            #size-cells = <1>;
>> +
>> +            qspi_boot1: partition@0 {
>> +                label = "Boot and fpga data";
>> +                reg = <0x0 0x10000000>;
>> +            };
>> +        };
>> +    };
>> +
>> +    flash@2 {
>> +        compatible = "micron,mt25qu02g", "jedec,spi-nor";
>> +        reg = <2>;
>> +        spi-max-frequency = <25000000>;
>> +
>> +        m25p,fast-read;
>> +        cdns,read-delay = <2>;
>> +        cdns,tshsl-ns = <50>;
>> +        cdns,tsd2d-ns = <50>;
>> +        cdns,tchsh-ns = <4>;
>> +        cdns,tslch-ns = <4>;
>> +        spi-tx-bus-width = <4>;
>> +        spi-rx-bus-width = <4>;
>> +
>> +        partitions {
>> +            compatible = "fixed-partitions";
>> +            #address-cells = <1>;
>> +            #size-cells = <1>;
>> +
>> +            qspi_boot2: partition@0 {
>> +                label = "Boot and fpga data";
>> +                reg = <0x0 0x10000000>;
>> +            };
>> +        };
>> +    };
>> +
>> +    flash@3 {
>> +        compatible = "micron,mt25qu02g", "jedec,spi-nor";
>> +        reg = <3>;
>> +        spi-max-frequency = <25000000>;
>> +
>> +        m25p,fast-read;
>> +        cdns,read-delay = <2>;
>> +        cdns,tshsl-ns = <50>;
>> +        cdns,tsd2d-ns = <50>;
>> +        cdns,tchsh-ns = <4>;
>> +        cdns,tslch-ns = <4>;
>> +        spi-tx-bus-width = <4>;
>> +        spi-rx-bus-width = <4>;
>> +
>> +        partitions {
>> +            compatible = "fixed-partitions";
>> +            #address-cells = <1>;
>> +            #size-cells = <1>;
>> +
>> +            qspi_boot3: partition@0 {
>> +                label = "Boot and fpga data";
> 
> Sashiko's comment on this is valid. You give these label a unique name,
> "Boot and fpga data 3"
> 
> 
> Dinh

Agreed. I'll make the labels unique in v4. flash@0 keeps "Boot and
fpga data" since U-Boot's RSU code looks up the boot partition on CS0
by that exact label.
flash@1-3 become "Boot and fpga data 1", "2" and "3".

-- 
Thanks,
Genevieve Chan