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([2a05:6e02:1041:c10:d71e:6d83:9df1:6316]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48150bf5f1csm6564893f8f.8.2026.08.12.02.56.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Aug 2026 02:56:04 -0700 (PDT) Message-ID: <9e9003b7-0331-4b37-9b06-5e9de887199e@oss.qualcomm.com> Date: Wed, 12 Aug 2026 11:56:03 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] clocksource/drivers/sun4i: Wait for pending reload before CTRL write To: =?UTF-8?Q?Ond=C5=99ej_Jirman?= , linux-sunxi@lists.linux.dev Cc: linux-kernel@vger.kernel.org, Daniel Lezcano , Thomas Gleixner , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Maxime Ripard , "moderated list:ARM/Allwinner sunXi SoC support" References: <20260725113341.2250687-1-megi@xff.cz> Content-Language: en-US From: Daniel Lezcano In-Reply-To: <20260725113341.2250687-1-megi@xff.cz> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=a8EAM0SF c=1 sm=1 tr=0 ts=6a7c4336 cx=c_pps a=7E5Bxpl4vBhpaufnMqZlrw==:117 a=xqWC_Br6kY4A:10 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=okeiRmupSayk4YNt53QA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=pJ04lnu7RYOZP9TFuWaZ:22 X-Proofpoint-ORIG-GUID: SMn9hREqhLkbeYvjn1dLHkx265__qcH_ X-Proofpoint-GUID: SMn9hREqhLkbeYvjn1dLHkx265__qcH_ X-Proofpoint-Spam-Info: AW1haW4tMjYwODEyMDA3OSBTYWx0ZWRfXzrja1GaW+sgv F1KZbGuX1qIVpLfEsXL/YAvHXj1952exKFVxjy2HnwoahTwR7OqsS6IVQbN5oN4nng3jDHHuDOb o7feQj2aEPrp2IVJL8yDpnSLNYRb4II= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODEyMDA3OSBTYWx0ZWRfX57Sp9Ww6wLPr Ukp3VgljMVTGGZjRYaKgeeOsq1fkz3vGn1yU8lbtKQ+Ng0HXuxC5q9a1ZEvQ8L2rUyfJpAzyp2m 7WS2n6VqckRe1UsOBWwvVrjSo5PcJ92ht9Pe5jXYklkVaTwKpl3OMeN/8aQaKmbU08FpzSb9x5W BtjKbgro8/H+V/fZnUAMViTO6tM0RN8RsVEGSz/GRMRZ3QxLqjFbQh79y5YezRa7G3Xh2gKognL hWWt7EcAkDvKkKcCL3tItFhSxIHoxiJes4/7vjRm/WkcfjLGNKj0g+wJI/oLsAWoqF6mMINSlAi k/wmIfbBhJwbmmfBZYQndZD0/PzOyck0mGX18ThA4cfp1NSNnMyL1uhjeBtWClwuhvvISmBqzhx sj0q4gXNqUB1tzQYVHP3Z4mgJb4nf0mQQUITaq9ab5QOivFLmdI4tUBDd3FK9mrwIQ/ge6lmqXx +HjWU5pm3YJXMiB66Kg== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-12_03,2026-08-10_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 suspectscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 adultscore=0 spamscore=0 malwarescore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608120079 On 7/25/26 13:33, Ondřej Jirman wrote: > From: Ondrej Jirman > > The A13 manual says of TMR0_RELOAD: "After the bit is set, it can not be > written again before it's cleared automatically." Both time_stop() and > time_start() read-modify-write the control register, so a reload still in > flight gets rewritten and the write can be dropped, leaving the timer > unarmed. In oneshot mode this happens on every tick, and the tick > eventually stops for good. > > Wait for the reload to clear first. All control register updates go > through sun4i_clkevt_time_stop(). > > Without this my Allwinner A13 based Pocketbook Touch Lux 3 stops > scheduling processes during boot or within a few seconds of executing > userspace. Only sysrq+t over serial port works at this stage, which is > how I discovered the root cause. > > Fixes: 7e14183469d8 ("clocksource: sun4i: Fix bug when switching from periodic to oneshot modes") > Signed-off-by: Ondrej Jirman > --- > BTW, similar issue will likely be also in timer-sun5i.c but I don't have any > device that would exercise it. And it's possible that this triggers more easily > with CONFIG_HZ=1000 which I use. > > drivers/clocksource/timer-sun4i.c | 26 +++++++++++++++++++++++++- > 1 file changed, 25 insertions(+), 1 deletion(-) > > diff --git a/drivers/clocksource/timer-sun4i.c b/drivers/clocksource/timer-sun4i.c > index 7bdcc60ad43c..2e7457f671c4 100644 > --- a/drivers/clocksource/timer-sun4i.c > +++ b/drivers/clocksource/timer-sun4i.c > @@ -39,6 +39,9 @@ > > #define TIMER_SYNC_TICKS 3 > > +/* The reload bit clears a couple of source clock cycles after it is set. */ > +#define TIMER_RELOAD_MAX_POLL 100 > + > /* > * When we disable a timer, we need to wait at least for 2 cycles of > * the timer source clock. We will use for that the clocksource timer > @@ -53,9 +56,30 @@ static void sun4i_clkevt_sync(void __iomem *base) > cpu_relax(); > } > > +/* > + * The control register must not be written while a reload is still in > + * flight, or the write can be dropped. > + */ > +static int sun4i_clkevt_wait_reload(void __iomem *base, u8 timer) > +{ > + int i; > + > + for (i = 0; i < TIMER_RELOAD_MAX_POLL; i++) { > + if (!(readl(base + TIMER_CTL_REG(timer)) & TIMER_CTL_RELOAD)) > + return 0; > + cpu_relax(); > + } The loop looks correct but I'm wondering why not use the helper: ret = readl_poll_timeout_atomic(base + TIMER_CTL_REG(timer), val, !(val & TIMER_CTL_RELOAD), 0, timeout); > + return -ETIME; > +} > + > static void sun4i_clkevt_time_stop(void __iomem *base, u8 timer) > { > - u32 val = readl(base + TIMER_CTL_REG(timer)); > + u32 val; > + > + sun4i_clkevt_wait_reload(base, timer); If it fails ? > + > + val = readl(base + TIMER_CTL_REG(timer)); > writel(val & ~TIMER_CTL_ENABLE, base + TIMER_CTL_REG(timer)); > sun4i_clkevt_sync(base); > }