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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from BL4PR12MB9505.namprd12.prod.outlook.com (2603:10b6:208:591::16) by CH0PR12MB8530.namprd12.prod.outlook.com (2603:10b6:610:188::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.522.13; Mon, 19 Oct 2026 17:14:27 +0000 Received: from BL4PR12MB9505.namprd12.prod.outlook.com ([fe80::73aa:eb8c:a86b:5a83]) by BL4PR12MB9505.namprd12.prod.outlook.com ([fe80::73aa:eb8c:a86b:5a83%5]) with mapi id 15.21.0522.017; Mon, 19 Oct 2026 17:14:27 +0000 Message-ID: <9eb8ccad-3919-4676-a3f7-6f7b2479d2ea@amd.com> Date: Mon, 19 Oct 2026 22:44:08 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 10/24] iommu/amd: Pass iommu to device_flush_dte() To: Suravee Suthikulpanit , linux-kernel@vger.kernel.org, iommu@lists.linux.dev, joro@8bytes.org, jgg@nvidia.com Cc: yi.l.liu@intel.com, kevin.tian@intel.com, nicolinc@nvidia.com, jon.grimm@amd.com, santosh.shukla@amd.com, Sairaj.K@amd.com, jay.chen@amd.com, Ming.Shu@amd.com, SooJin.Tan@amd.com, chrisl@kernel.org, wvw@google.com, wnliu@google.com, dantuluris@google.com, kpsingh@google.com, alejandro.j.jimenez@oracle.com, joao.m.martins@oracle.com, guanghuifeng@linux.alibaba.com References: <20260930092344.5616-1-suravee.suthikulpanit@amd.com> <20260930092344.5616-11-suravee.suthikulpanit@amd.com> Content-Language: en-US From: Vasant Hegde In-Reply-To: <20260930092344.5616-11-suravee.suthikulpanit@amd.com> Content-Type: text/plain; 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Also, flush each device in > amd_iommu_change_top() immediately after updating its DTE. > > Reviewed-by: Jason Gunthorpe > Signed-off-by: Suravee Suthikulpanit > --- > drivers/iommu/amd/iommu.c | 13 +++++-------- > 1 file changed, 5 insertions(+), 8 deletions(-) > > diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c > index dfb9268f3c4e..a45044e1d423 100644 > --- a/drivers/iommu/amd/iommu.c > +++ b/drivers/iommu/amd/iommu.c > @@ -76,7 +76,7 @@ static void set_dte_entry(struct amd_iommu *iommu, > struct iommu_dev_data *dev_data, > phys_addr_t top_paddr, unsigned int top_level); > > -static int device_flush_dte(struct iommu_dev_data *dev_data); > +static int device_flush_dte(struct amd_iommu *iommu, struct iommu_dev_data *dev_data); > > static void amd_iommu_change_top(struct pt_iommu *iommu_table, > phys_addr_t top_paddr, unsigned int top_level); > @@ -218,7 +218,7 @@ void amd_iommu_update_dte(struct amd_iommu *iommu, > { > update_dte256(iommu, dev_data, new); > clone_aliases(iommu, dev_data->dev); > - device_flush_dte(dev_data); > + device_flush_dte(iommu, dev_data); > iommu_completion_wait(iommu); > } > > @@ -1824,9 +1824,8 @@ static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data) > /* > * Command send function for invalidating a device table entry > */ > -static int device_flush_dte(struct iommu_dev_data *dev_data) > +static int device_flush_dte(struct amd_iommu *iommu, struct iommu_dev_data *dev_data) > { > - struct amd_iommu *iommu = get_amd_iommu_from_dev_data(dev_data); > struct pci_dev *pdev = NULL; > struct amd_iommu_pci_seg *pci_seg; > u16 alias; > @@ -2795,11 +2794,9 @@ static void amd_iommu_change_top(struct pt_iommu *iommu_table, > /* Update the HW references with the new level and top ptr */ > set_dte_entry(iommu, dev_data, top_paddr, top_level); > clone_aliases(iommu, dev_data->dev); > + device_flush_dte(iommu, dev_data); May be an existing issue. set_dte_entry -> amd_iommu_update_dte() already handles clone_aliases and dte_flush. -Vasant