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Mon, 07 Sep 2026 03:42:21 -0700 (PDT) X-Received: by 2002:a17:90b:4c51:b0:38e:57a3:f218 with SMTP id 98e67ed59e1d1-39b26204e5bmr31098665a91.13.1788777741381; Mon, 07 Sep 2026 03:42:21 -0700 (PDT) Received: from [192.168.1.11] ([103.211.19.41]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1432424d27asm35559357c88.2.2026.09.07.03.42.14 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Sep 2026 03:42:20 -0700 (PDT) Message-ID: <9ebc94f1-3ed8-4a21-a84e-ccd46f044927@oss.qualcomm.com> Date: Mon, 7 Sep 2026 16:12:12 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/6] dt-bindings: media: qcom,glymur-camss: Add Glymur CAMSS To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Lee Jones , Guru Das Srinagesh , Liam Girdwood , Mark Brown Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mfd@lists.linux.dev, Suresh Vankadara , Vikram Sharma References: <20260907-glymur_camss-v2-0-75f7982dc983@oss.qualcomm.com> <20260907-glymur_camss-v2-2-75f7982dc983@oss.qualcomm.com> <3e619085-3311-4acd-9493-e849875563d7@kernel.org> Content-Language: en-US From: Nihal Kumar Gupta In-Reply-To: <3e619085-3311-4acd-9493-e849875563d7@kernel.org> Content-Type: text/plain; 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>> Glymur uses only the new PHY API via standalone phy@ child nodes, >> so per-CSIPHY clocks, interrupts and supplies are absent here. > > What's up with the commit log here ? There is no legacy CSIPHY in this.. ? > Right, Glymur has none — that's the point. X1E80100 supports both; camss_detect_legacy_phy() picks the path at runtime by checking if the remote endpoint is a phy@ node. Glymur is new-path only, hence a dedicated binding without those legacy properties. The example shows port@0/1/3 → csiphy0/1/4_out; port@2 is absent as CSIPHY2 does not exist on Glymur silicon. >> >> X1E80100 has four CSIPHY instances while Glymur has three >> (CSIPHY0, CSIPHY1, CSIPHY4), expressed entirely in DT.