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b=qR7xo0M1jt+EZKfVMDpy3HW1lsFcsIdufoKRZyekUE2P4ZDW8Okgu4Zl70JjrvcomP2Otu1Nt50efRXiE2cVJhyyKGTplcNQdbzisxPEorf39sb9EImxJdbU3b04KLEuQt7tlsLGD+/pZwSM4rQhRu8NF+0+vD/H2Ua+zcQhaVY= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from BL3PR12MB6642.namprd12.prod.outlook.com (2603:10b6:208:38e::15) by SJ1PR12MB6220.namprd12.prod.outlook.com (2603:10b6:a03:455::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8901.35; Mon, 14 Jul 2025 14:51:56 +0000 Received: from BL3PR12MB6642.namprd12.prod.outlook.com ([fe80::aacd:a6d8:e180:46bc]) by BL3PR12MB6642.namprd12.prod.outlook.com ([fe80::aacd:a6d8:e180:46bc%5]) with mapi id 15.20.8901.033; Mon, 14 Jul 2025 14:51:54 +0000 Message-ID: <9ee6ee78-af88-4b57-a939-30390c790972@amd.com> Date: Mon, 14 Jul 2025 08:51:51 -0600 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V1 4/9] dt-bindings: soc: xilinx: Add AI engine DT binding To: Krzysztof Kozlowski , Gregory Williams , ogabbay@kernel.org, michal.simek@amd.com, robh@kernel.org Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20250702155630.1737227-1-gregory.williams@amd.com> <20250702155630.1737227-5-gregory.williams@amd.com> <7533fd56-aeef-4685-a25f-d64b3f6a2d78@kernel.org> <504f6660-4938-47b4-b1db-0a6fe0214e5f@kernel.org> <349be13c-fef5-4fc2-b4c9-e85e28cbc06a@amd.com> <0c1e62fa-aec3-4d01-8fa0-d10817122426@kernel.org> Content-Language: en-US From: "Williams, Gregory" In-Reply-To: <0c1e62fa-aec3-4d01-8fa0-d10817122426@kernel.org> Content-Type: text/plain; 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The data routing between cores is configured through >>>>>> + internal switches, and shim tiles interface with external interconnect, such >>>>>> + as memory or PL. One AI engine device can have multiple apertures, each >>>>>> + has its own address space and interrupt. At runtime application can create >>>>>> + multiple partitions within an aperture which are groups of columns of AI >>>>>> + engine tiles. Each AI engine partition is the minimum resetable unit for an >>>>>> + AI engine application. >>>>>> + >>>>>> +properties: >>>>>> + compatible: >>>>>> + const: xlnx,ai-engine-v2.0 >>>>> >>>>> What does v2.0 stands for? Versioning is discouraged, unless mapping is >>>>> well documented. >>>> >>>> Sure, I will remove the versioning in V2 patch. >>> >>> This should be specific to product, so use the actual product/model name. >>> >>> Is this part of a Soc? Then standard rules apply... but I could not >>> deduce it from the descriptions or commit msgs. >> >> Yes this is part of an SoC. I will be more descriptive in V2 patch. > > Huh... so you MUST use SoC compatibles. Don't upstream things entirely > different than everything else. I will fix this in V2 patch. Thanks, Greg > > Best regards, > Krzysztof