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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by MW1PEPF0001615A.mail.protection.outlook.com (10.167.249.85) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.496.3 via Frontend Transport; Tue, 29 Sep 2026 22:39:15 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49; Tue, 29 Sep 2026 17:39:13 -0500 From: Babu Moger To: , , CC: , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 1/2] x86/resctrl: Rename AMD resctrl MSR defines to use MSR_AMD_ prefix Date: Tue, 29 Sep 2026 17:39:03 -0500 Message-ID: <9ef5ec08d79c9c84f36b11251bd3189af1a38d52.1790721445.git.babu.moger@amd.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW1PEPF0001615A:EE_|SA1PR12MB6776:EE_ X-MS-Office365-Filtering-Correlation-Id: 195b0b5b-8a43-4f61-e5cc-08df1e7a7de9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|1800799024|376014|82310400026|7416014|36860700016|13003099007|260925021911599003|260925022911599003|6133799003|10067099003|11063799006|260925021311599003|56012099006|18002099003; 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The MSR_IA32_ prefix is misleading when reading or grepping the codebase alongside the Intel MSR_IA32_* resctrl definitions in msr-index.h. Rename the AMD resctrl MSR definitions, update all call sites, and keep the tools copy of msr-index.h in sync: MSR_IA32_MBA_BW_BASE -> MSR_AMD_MBA_BW_BASE MSR_IA32_SMBA_BW_BASE -> MSR_AMD_SMBA_BW_BASE MSR_IA32_L3_QOS_ABMC_CFG -> MSR_AMD_L3_QOS_ABMC_CFG MSR_IA32_L3_QOS_EXT_CFG -> MSR_AMD_L3_QOS_EXT_CFG MSR_IA32_EVT_CFG_BASE -> MSR_AMD_EVT_CFG_BASE No functional changes. Suggested-by: Borislav Petkov (AMD) Signed-off-by: Babu Moger --- v2: Fixed few redundant 'MSR' texts. v1: https://lore.kernel.org/lkml/96992e30d6c02ebb7bdb58f2d8060bfd61274649.1784739398.git.babu.moger@amd.com/ --- arch/x86/include/asm/msr-index.h | 10 +++++----- arch/x86/kernel/cpu/resctrl/core.c | 4 ++-- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 6 +++--- arch/x86/kernel/cpu/resctrl/internal.h | 6 +++--- arch/x86/kernel/cpu/resctrl/monitor.c | 8 ++++---- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 4 ++-- fs/resctrl/rdtgroup.c | 4 ++-- tools/arch/x86/include/asm/msr-index.h | 10 +++++----- 8 files changed, 26 insertions(+), 26 deletions(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 82ca6356dc62..7998fd116aa8 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1302,11 +1302,11 @@ #define MSR_IA32_MBA_THRTL_BASE 0xd50 /* - AMD: */ -#define MSR_IA32_MBA_BW_BASE 0xc0000200 -#define MSR_IA32_SMBA_BW_BASE 0xc0000280 -#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd -#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff -#define MSR_IA32_EVT_CFG_BASE 0xc0000400 +#define MSR_AMD_MBA_BW_BASE 0xc0000200 +#define MSR_AMD_SMBA_BW_BASE 0xc0000280 +#define MSR_AMD_L3_QOS_ABMC_CFG 0xc00003fd +#define MSR_AMD_L3_QOS_EXT_CFG 0xc00003ff +#define MSR_AMD_EVT_CFG_BASE 0xc0000400 /* AMD-V MSRs */ #define MSR_VM_CR 0xc0010114 diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 55214d6fdc49..a7c2210859f8 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -1055,10 +1055,10 @@ static __init void rdt_init_res_defs_amd(void) r->cache.arch_has_per_cpu_cfg = true; r->cache.min_cbm_bits = 0; } else if (r->rid == RDT_RESOURCE_MBA) { - hw_res->msr_base = MSR_IA32_MBA_BW_BASE; + hw_res->msr_base = MSR_AMD_MBA_BW_BASE; hw_res->msr_update = mba_wrmsr_amd; } else if (r->rid == RDT_RESOURCE_SMBA) { - hw_res->msr_base = MSR_IA32_SMBA_BW_BASE; + hw_res->msr_base = MSR_AMD_SMBA_BW_BASE; hw_res->msr_update = mba_wrmsr_amd; } } diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c index 62044489b052..25a5f0c8dc56 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -108,9 +108,9 @@ static void resctrl_sdciae_set_one_amd(void *arg) bool *enable = arg; if (*enable) - msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); + msr_set_bit(MSR_AMD_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); else - msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); + msr_clear_bit(MSR_AMD_L3_QOS_EXT_CFG, SDCIAE_ENABLE_BIT); } static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable) @@ -120,7 +120,7 @@ static void _resctrl_sdciae_enable(struct rdt_resource *r, bool enable) /* Walking r->ctrl_domains, ensure it can't race with cpuhp */ lockdep_assert_cpus_held(); - /* Update MSR_IA32_L3_QOS_EXT_CFG MSR on all the CPUs in all domains */ + /* Update MSR_AMD_L3_QOS_EXT_CFG on all the CPUs in all domains */ list_for_each_entry_rcu(d, &r->ctrl_domains, hdr.list, lockdep_is_cpus_held()) on_each_cpu_mask(&d->hdr.cpu_mask, resctrl_sdciae_set_one_amd, &enable, 1); } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index e3cfa0c10e92..18d9558e944a 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -40,7 +40,7 @@ struct arch_mbm_state { u64 prev_msr; }; -/* Setting bit 0 in L3_QOS_EXT_CFG enables the ABMC feature. */ +/* Setting bit 0 in MSR_AMD_L3_QOS_EXT_CFG enables the ABMC feature. */ #define ABMC_ENABLE_BIT 0 /* @@ -49,7 +49,7 @@ struct arch_mbm_state { #define ABMC_EXTENDED_EVT_ID BIT(31) #define ABMC_EVT_ID BIT(0) -/* Setting bit 1 in MSR_IA32_L3_QOS_EXT_CFG enables the SDCIAE feature. */ +/* Setting bit 1 in MSR_AMD_L3_QOS_EXT_CFG enables the SDCIAE feature. */ #define SDCIAE_ENABLE_BIT 1 /** @@ -187,7 +187,7 @@ union cpuid_0x10_x_edx { }; /* - * ABMC counters are configured by writing to MSR_IA32_L3_QOS_ABMC_CFG. + * ABMC counters are configured by writing to MSR_AMD_L3_QOS_ABMC_CFG. * * @bw_type : Event configuration that represents the memory * transactions being tracked by the @cntr_id. diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index 3838e0a13d36..c6036b09a67f 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -498,13 +498,13 @@ static void resctrl_abmc_set_one_amd(void *arg) bool *enable = arg; if (*enable) - msr_set_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); + msr_set_bit(MSR_AMD_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); else - msr_clear_bit(MSR_IA32_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); + msr_clear_bit(MSR_AMD_L3_QOS_EXT_CFG, ABMC_ENABLE_BIT); } /* - * ABMC enable/disable requires update of L3_QOS_EXT_CFG MSR on all the CPUs + * ABMC enable/disable requires update of MSR_AMD_L3_QOS_EXT_CFG on all the CPUs * associated with all monitor domains. */ static void _resctrl_abmc_enable(struct rdt_resource *r, bool enable) @@ -542,7 +542,7 @@ static void resctrl_abmc_config_one_amd(void *info) { union l3_qos_abmc_cfg *abmc_cfg = info; - wrmsrq(MSR_IA32_L3_QOS_ABMC_CFG, abmc_cfg->full); + wrmsrq(MSR_AMD_L3_QOS_ABMC_CFG, abmc_cfg->full); } /* diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 5ffa39fa86fa..6590ebf6b29d 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -96,7 +96,7 @@ void resctrl_arch_mon_event_config_read(void *_config_info) pr_warn_once("Invalid event id %d\n", config_info->evtid); return; } - rdmsrq(MSR_IA32_EVT_CFG_BASE + index, msrval); + rdmsrq(MSR_AMD_EVT_CFG_BASE + index, msrval); /* Report only the valid event configuration bits */ config_info->mon_config = msrval & MAX_EVT_CONFIG_BITS; @@ -112,7 +112,7 @@ void resctrl_arch_mon_event_config_write(void *_config_info) pr_warn_once("Invalid event id %d\n", config_info->evtid); return; } - wrmsrq(MSR_IA32_EVT_CFG_BASE + index, config_info->mon_config); + wrmsrq(MSR_AMD_EVT_CFG_BASE + index, config_info->mon_config); } static void l3_qos_cfg_update(void *arg) diff --git a/fs/resctrl/rdtgroup.c b/fs/resctrl/rdtgroup.c index 68be9b903ac6..552ec06886f6 100644 --- a/fs/resctrl/rdtgroup.c +++ b/fs/resctrl/rdtgroup.c @@ -1794,8 +1794,8 @@ static void mbm_config_write_domain(struct rdt_resource *r, mon_info.mon_config = val; /* - * Update MSR_IA32_EVT_CFG_BASE MSR on one of the CPUs in the - * domain. The MSRs offset from MSR MSR_IA32_EVT_CFG_BASE + * Update MSR_AMD_EVT_CFG_BASE on one of the CPUs in the + * domain. The MSRs offset from MSR_AMD_EVT_CFG_BASE * are scoped at the domain level. Writing any of these MSRs * on one CPU is observed by all the CPUs in the domain. */ diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h index 18c4be75e927..b68ad3088779 100644 --- a/tools/arch/x86/include/asm/msr-index.h +++ b/tools/arch/x86/include/asm/msr-index.h @@ -1290,11 +1290,11 @@ #define MSR_IA32_MBA_THRTL_BASE 0xd50 /* - AMD: */ -#define MSR_IA32_MBA_BW_BASE 0xc0000200 -#define MSR_IA32_SMBA_BW_BASE 0xc0000280 -#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd -#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff -#define MSR_IA32_EVT_CFG_BASE 0xc0000400 +#define MSR_AMD_MBA_BW_BASE 0xc0000200 +#define MSR_AMD_SMBA_BW_BASE 0xc0000280 +#define MSR_AMD_L3_QOS_ABMC_CFG 0xc00003fd +#define MSR_AMD_L3_QOS_EXT_CFG 0xc00003ff +#define MSR_AMD_EVT_CFG_BASE 0xc0000400 /* AMD-V MSRs */ #define MSR_VM_CR 0xc0010114 -- 2.43.0