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X-OriginatorOrg: phytec.de X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Nov 2024 12:53:00.9337 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: af870ffc-6b7b-49ed-2257-08dd09624412 X-MS-Exchange-CrossTenant-Id: e609157c-80e2-446d-9be3-9c99c2399d29 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e609157c-80e2-446d-9be3-9c99c2399d29;Ip=[91.26.50.189];Helo=[Diagnostix.phytec.de] X-MS-Exchange-CrossTenant-AuthSource: DU6PEPF00009524.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8P195MB1846 Am 13.11.24 um 12:09 schrieb MD Danish Anwar: > ICSSG has 7 available clocks per instance. Add all the cloks to ICSSG > nodes. ICSSG currently uses ICSSG_ICLK (clk id 20) which operates at > 250MHz. Switch ICSSG clock to ICSSG_CORE clock (clk id 0) which operates at > 333MHz. > > ICSSG_CORE clock will help get the most out of ICSSG as more cycles are > needed to fully support all ICSSG features. > > This commit also changes assigned-clock-parents of coreclk-mux to > ICSSG_CORE clock from ICSSG_ICLK. > > Performance update in dual mac mode > With ICSSG_CORE Clk @ 333MHz > Tx throughput - 934 Mbps > Rx throughput - 914 Mbps, > > With ICSSG_ICLK clk @ 250MHz, > Tx throughput - 920 Mbps > Rx throughput - 706 Mbps I can see similar improvements. Thank you. > > Signed-off-by: MD Danish Anwar Tested on a phyBOARD-Electra-AM64x board, Tested-by: Wadim Egorov