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Fri, 09 Aug 2024 15:24:52 +0000 (GMT) Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.17.1.19/8.17.1.19) with ESMTPS id 479FOofS014765 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 9 Aug 2024 15:24:50 GMT Received: from [10.110.23.148] (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 9 Aug 2024 08:24:50 -0700 Message-ID: <9f017342-b686-4ba0-bb0a-6912b051c152@quicinc.com> Date: Fri, 9 Aug 2024 08:24:50 -0700 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 01/10] accel/amdxdna: Add a new driver for AMD AI Engine To: Lizhi Hou , , CC: , , , , , Narendra Gutta , George Yang References: <20240805173959.3181199-1-lizhi.hou@amd.com> <20240805173959.3181199-2-lizhi.hou@amd.com> From: Carl Vanderlip Content-Language: en-US In-Reply-To: <20240805173959.3181199-2-lizhi.hou@amd.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: ym8JSr7mrvEhegnRW_fBAFHwV1HpaJlH X-Proofpoint-GUID: ym8JSr7mrvEhegnRW_fBAFHwV1HpaJlH X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-09_12,2024-08-07_01,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 adultscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 phishscore=0 suspectscore=0 impostorscore=0 clxscore=1011 spamscore=0 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408090111 On 8/5/2024 10:39 AM, Lizhi Hou wrote: > +static int aie2_init(struct amdxdna_dev *xdna) > +{ > + struct pci_dev *pdev = to_pci_dev(xdna->ddev.dev); > + struct amdxdna_dev_hdl *ndev; > + struct psp_config psp_conf; > + const struct firmware *fw; > + void __iomem * const *tbl; > + int i, bars, nvec, ret; > + > + ndev = devm_kzalloc(&pdev->dev, sizeof(*ndev), GFP_KERNEL); > + if (!ndev) > + return -ENOMEM; > + > + ndev->priv = xdna->dev_info->dev_priv; > + ndev->xdna = xdna; > + > + ret = request_firmware(&fw, ndev->priv->fw_path, &pdev->dev); > + if (ret) { > + XDNA_ERR(xdna, "failed to request_firmware %s, ret %d", > + ndev->priv->fw_path, ret); > + return ret; > + } > + > + ret = pcim_enable_device(pdev); Does request_firmware need to be the first thing here? Its not used until the end of init. Likewise, fw image is copied in *_create, but then not released until after *_hw_start; could release_firmware more closely wrap where it is used? I could see it being checked first because if the fw isn't there, what's the point, but that could be said about any of the other resources here. On 8/5/2024 10:39 AM, Lizhi Hou wrote: > +enum aie2_smu_reg_idx { > + SMU_CMD_REG = 0, > + SMU_ARG_REG, > + SMU_INTR_REG, > + SMU_RESP_REG, > + SMU_OUT_REG, > + SMU_MAX_REGS /* Kepp this at the end */ > +}; *Keep -Carl V. PS Sorry for double email Lizhi, forgot to send to list.