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[188.155.185.9]) by smtp.gmail.com with ESMTPSA id s7sm15631663wrf.91.2021.06.07.01.28.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 07 Jun 2021 01:28:15 -0700 (PDT) Subject: Re: [PULL] memory: tegra: Changes for v5.14-rc1 To: Dmitry Osipenko , Thierry Reding Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org References: <20210603143739.787957-1-thierry.reding@gmail.com> <772bf62a-fb09-cec4-ed4d-ddbfc2832e2b@gmail.com> <3ed358ce-de98-0b42-2446-873af55ed825@gmail.com> From: Krzysztof Kozlowski Message-ID: <9f1fe71e-3900-fa8a-8c09-4bc2dc084156@canonical.com> Date: Mon, 7 Jun 2021 10:28:14 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.8.1 MIME-Version: 1.0 In-Reply-To: <3ed358ce-de98-0b42-2446-873af55ed825@gmail.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 04/06/2021 14:51, Dmitry Osipenko wrote: > 04.06.2021 12:32, Thierry Reding пишет: >> On Thu, Jun 03, 2021 at 10:56:29PM +0300, Dmitry Osipenko wrote: >>> 03.06.2021 17:37, Thierry Reding пишет: >>>> memory: tegra: Changes for v5.14-rc1 >>>> >>>> This stable tag contains Dmitry's power domain work, including all the >>>> necessary dependencies from the regulator, clock and ARM SoC trees. >>>> >>>> ---------------------------------------------------------------- >>>> Dmitry Osipenko (18): >>>> clk: tegra30: Use 300MHz for video decoder by default >>>> clk: tegra: Fix refcounting of gate clocks >>>> clk: tegra: Ensure that PLLU configuration is applied properly >>>> clk: tegra: Halve SCLK rate on Tegra20 >>>> clk: tegra: Don't allow zero clock rate for PLLs >>>> clk: tegra: cclk: Handle thermal DIV2 CPU frequency throttling >>>> clk: tegra: Mark external clocks as not having reset control >>>> clk: tegra: Don't deassert reset on enabling clocks >>>> regulator: core: Add regulator_sync_voltage_rdev() >>> >>>> soc/tegra: regulators: Bump voltages on system reboot >>> >>> This patch is a build dependency prerequisite for the "soc/tegra: >>> regulators: Support core domain state syncing" patch. Will you send a >>> new PR to Krzysztof with the remaining soc/tegra patches? >> >> soc/tegra patches usually go in through ARM SoC. This is merely included >> here because it was part of the set of patches that were needed to >> enable compile testing for the memory controller drivers. >> >> I've applied the remaining soc/tegra patches (12-14 of the series) to my >> for-5.14/soc branch but ended up not pulling that part in because it was >> unnecessary for the memory controller patches. > > Does this mean that if for-5.14/soc will be pulled first into mainline, > then the patches will be applied in a wrong order? All of the branches of each maintainer should be bisectable, so order of pulling by Linus' should not matter. Assuming current Thierry's branches are bisectable, how Linus' tree can be broken after specific pull order? Best regards, Krzysztof