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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 5614622812f47-3f19da6eab9sm3330497b6e.17.2025.01.21.16.16.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Jan 2025 16:16:32 -0800 (PST) Message-ID: <9f40295b-484a-48e8-b053-ff8550e589d7@baylibre.com> Date: Tue, 21 Jan 2025 18:16:32 -0600 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/7] dt-bindings: spi: zynqmp-qspi: Split the bus To: Sean Anderson , Mark Brown , Michal Simek , linux-spi@vger.kernel.org Cc: Jinjie Ruan , linux-arm-kernel@lists.infradead.org, Amit Kumar Mahapatra , linux-kernel@vger.kernel.org, Miquel Raynal , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, "linux-iio@vger.kernel.org" , Jonathan Cameron , =?UTF-8?Q?Nuno_S=C3=A1?= References: <20250116232118.2694169-1-sean.anderson@linux.dev> <20250116232118.2694169-2-sean.anderson@linux.dev> From: David Lechner Content-Language: en-US In-Reply-To: <20250116232118.2694169-2-sean.anderson@linux.dev> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/16/25 5:21 PM, Sean Anderson wrote: > This device supports two separate SPI busses: ... > @@ -84,5 +94,32 @@ examples: > resets = <&zynqmp_reset ZYNQMP_RESET_QSPI>; > reg = <0x0 0xff0f0000 0x0 0x1000>, > <0x0 0xc0000000 0x0 0x8000000>; > + > + spi-lower { > + #address-cells = <1>; > + #size-cells = <0>; > + num-cs = <2>; > + cs-gpios = <0>, <&gpio 5>; > + > + flash@0 { > + reg = <0>; > + compatible = "jedec,spi-nor"; > + }; > + > + flash@1 { > + reg = <1>; > + compatible = "jedec,spi-nor"; > + }; > + }; > + > + spi-upper { > + #address-cells = <1>; > + #size-cells = <0>; > + > + flash@0 { > + reg = <0>; > + compatible = "jedec,spi-nor"; > + }; > + }; > }; > }; In the IIO subsystem, we've been recently working on several "advanced" ADCs that could use a SPI controller like this. These ADCs have multiple input channels that perform conversions in parallel and the data for each channel needs to be read back on a separate serial line (MISO) at the same time. Another similar case is to have two separate chips, but they share a conversion trigger and essentially operate as a single composite device rather than two distinct devices [1]. This would be similar to some ADCs that are daisy-chained where we consider all of the chips in the chain as a single composite device, but they would be in parallel rather than chained. [1]: https://lore.kernel.org/linux-iio/e5e8eba7-2455-488b-a36f-e246844e11fd@baylibre.com/ For those use cases though, as mentioned above, we only have a single device that would be connected to both buses. So for such a SPI controller with multiple buses, I was envisioning that instead of adding child nodes for each of the child buses, that we would do something like add a spi-buses property to the spi peripheral bindings where you could specify one or more buses that a device was connected to. e.g. a device connected to the lower bus would be spi-buses = <0>; one connected to the upper bus would be spi-buses = <1>; and a device connected to both would be spi-buses = <0>, <1>;. This would also work for SPI controllers that have 4 or 8 busses. SPI controllers like these have a striping feature that allows to control both buses at the same to either mirror the same data on both buses at the same time when writing, e.g. for configuration or to read and write two different bytes at the same time. A peripheral driver for device that was connected to both buses could make use of this feature to craft a single SPI message with transfers containing (new) parameters that specify which bus to use (one or both) and, in the case of using both buses, to mirror or stripe the data. Could we make a single device connected to both buses like this work using the proposed spi-lower and spi-upper or should we consider a different binding like the one I suggested?