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Mon, 26 Feb 2024 09:27:04 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 54A3840047; Mon, 26 Feb 2024 09:27:01 +0100 (CET) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id B2CC424DFE9; Mon, 26 Feb 2024 09:26:32 +0100 (CET) Received: from [10.201.21.177] (10.201.21.177) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.27; Mon, 26 Feb 2024 09:26:31 +0100 Message-ID: <9fb17963-8942-4810-ae86-508fd7b3466a@foss.st.com> Date: Mon, 26 Feb 2024 09:26:31 +0100 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/5] memory: stm32-fmc2-ebi: add MP25 support Content-Language: en-US To: Krzysztof Kozlowski , , , CC: , , References: <20240219140202.85680-1-christophe.kerello@foss.st.com> <20240219140202.85680-4-christophe.kerello@foss.st.com> <21ad2752-ad25-451a-b892-6b3b31c1031a@linaro.org> From: Christophe Kerello In-Reply-To: <21ad2752-ad25-451a-b892-6b3b31c1031a@linaro.org> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-26_05,2024-02-23_01,2023-05-22_02 Hi Krzysztof, On 2/21/24 09:32, Krzysztof Kozlowski wrote: > On 19/02/2024 15:02, Christophe Kerello wrote: >> Add the support of the revision 2 of FMC2 IP. >> - PCSCNTR register has been removed, >> - CFGR register has been added, >> - the bit used to enable the IP has moved from BCR1 to CFGR, >> - the timeout for CEx deassertion has moved from PCSCNTR to BCRx, >> - the continuous clock enable has moved from BCR1 to CFGR, >> - the clk divide ratio has moved from BCR1 to CFGR. >> >> The MP1 SoCs have only one signal to manage all the controllers (NWAIT). >> The MP25 SOC has one RNB signal for the NAND controller and one NWAIT >> signal for the memory controller. >> >> Let's use a platform data structure for parameters that will differ >> between MP1 and MP25. > > > ... > >> + >> ebi->regmap = device_node_to_regmap(dev->of_node); >> if (IS_ERR(ebi->regmap)) >> return PTR_ERR(ebi->regmap); >> @@ -1190,9 +1502,11 @@ static int stm32_fmc2_ebi_probe(struct platform_device *pdev) >> if (ret) >> goto err_release; >> >> - ret = stm32_fmc2_ebi_save_setup(ebi); >> - if (ret) >> - goto err_release; >> + if (ebi->data->save_setup) { > > This cannot be NULL. Ok, it will be done in V3. Regards, Christophe Kerello. > >> + ret = ebi->data->save_setup(ebi); >> + if (ret) >> + goto err_release; >> + } >> >> platform_set_drvdata(pdev, ebi); >> >> @@ -1238,7 +1552,9 @@ static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev) >> if (ret) >> return ret; >> >> - stm32_fmc2_ebi_set_setup(ebi); >> + if (ebi->data->set_setup) > > This cannot be NULL. > > > > Best regards, > Krzysztof >