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AJvYcCWWoaHkJCVwK04TWkIAg2eTbGP0okhlM2TC87s76E3/chDniwYnLxeVaxG0K73zbnda854efBJ8z60dXDs=@vger.kernel.org X-Gm-Message-State: AOJu0Yy1b0003BIJWwONaBmjldVG3IRE93gRfkNLvql9jM+RouXT1tqp /wFWsnvV0C440tlvqY/tsF/IG6te54D11fu1JWhLXbp2AUifWLnd7TQOowhUJFA= X-Gm-Gg: ASbGncsHlGSjxPHbLbaSusZid71qT611feg1JQpym1kjAiz47mI6VjuSGXVn21KLkhZ jvnlEcR/DIfqVUzasUw7AYbvbIWvDC1dvWen4aVniDBTJsK6Fs8ohS5FIXt4MYCr+Jca2kv7+cH nYhem2GRQNeA/9PF6WTROMMQ1Sxu2Ld0jlzUjMM3yc46PL8Q6PoR1oih8hJuLosuEmxnUqxacX/ KmrZO4sW8GfNv9xpBDOBnfjxLiBpJQ6L8q4ICRjUdWNQV8UpeL4JwQsTw0= X-Google-Smtp-Source: AGHT+IGgMEMrSAPr02MLIHAcIHPoTg9MNMPJ2rKs998sfhdc8FiMJuyQZbDGm5o1c5USrCVKcB7FqQ== X-Received: by 2002:a17:906:2189:b0:aa6:74a9:ce6e with SMTP id a640c23a62f3a-aa674a9d065mr269789166b.16.1733675398372; Sun, 08 Dec 2024 08:29:58 -0800 (PST) Received: from [192.168.50.4] ([82.78.167.161]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aa68a97498dsm5949966b.99.2024.12.08.08.29.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 08 Dec 2024 08:29:57 -0800 (PST) Message-ID: <9fbbf3d1-9543-42f8-a80c-1527811109ef@tuxon.dev> Date: Sun, 8 Dec 2024 18:29:55 +0200 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 09/13] ARM: dts: microchip: add sama7d65 SoC DT Content-Language: en-US From: Claudiu Beznea To: Ryan.Wanner@microchip.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, nicolas.ferre@microchip.com, alexandre.belloni@bootlin.com, mturquette@baylibre.com, sboyd@kernel.org, arnd@arndb.de Cc: dharma.b@microchip.com, mihai.sain@microchip.com, romain.sioen@microchip.com, varshini.rajendran@microchip.com, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org, linux-serial@vger.kernel.org References: <9a6c1dfe-cf4d-41fc-a0f4-b6a111a40c94@tuxon.dev> In-Reply-To: <9a6c1dfe-cf4d-41fc-a0f4-b6a111a40c94@tuxon.dev> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 08.12.2024 18:28, Claudiu Beznea wrote: > > > On 06.12.2024 21:59, Ryan.Wanner@microchip.com wrote: >> From: Ryan Wanner >> >> Add Device Tree for sama7d65 SoC. >> >> Co-developed-by: Dharma Balasubiramani >> Signed-off-by: Dharma Balasubiramani >> Co-developed-by: Romain Sioen >> Signed-off-by: Romain Sioen >> Co-developed-by: Varshini Rajendran >> Signed-off-by: Varshini Rajendran >> Signed-off-by: Ryan Wanner >> --- >> arch/arm/boot/dts/microchip/sama7d65.dtsi | 145 ++++++++++++++++++++++ >> 1 file changed, 145 insertions(+) >> create mode 100644 arch/arm/boot/dts/microchip/sama7d65.dtsi >> >> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi >> new file mode 100644 >> index 000000000000..0dcd80690210 >> --- /dev/null >> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi >> @@ -0,0 +1,145 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * sama7d65.dtsi - Device Tree Include file for SAMA7D65 SoC >> + * >> + * Copyright (C) 2024 Microchip Technology, Inc. and its subsidiaries >> + * >> + * Author: Ryan Wanner >> + * >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +/ { >> + model = "Microchip SAMA7D65 family SoC"; >> + compatible = "microchip,sama7d65"; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + interrupt-parent = <&gic>; >> + >> + cpus { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + cpu0: cpu@0 { >> + compatible = "arm,cortex-a7"; >> + reg = <0x0>; >> + device_type = "cpu"; >> + clocks = <&pmc PMC_TYPE_CORE PMC_CPUPLL>; >> + clock-names = "cpu"; >> + }; >> + }; >> + >> + clocks { >> + main_xtal: clock-mainxtal { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + }; >> + >> + slow_xtal: clock-slowxtal { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + }; >> + >> + }; >> + >> + soc { >> + compatible = "simple-bus"; >> + ranges; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + >> + pioa: pinctrl@e0014000 { >> + compatible = "microchip,sama7d65-pinctrl"; >> + reg = <0xe0014000 0x800>; >> + interrupts = , >> + , >> + , >> + , >> + ; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + gpio-controller; >> + #gpio-cells = <2>; >> + }; >> + >> + pmc: clock-controller@e0018000 { >> + compatible = "microchip,sama7d65-pmc", "syscon"; >> + reg = <0xe0018000 0x200>; >> + interrupts = ; >> + #clock-cells = <2>; >> + clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; >> + clock-names = "td_slck", "md_slck", "main_xtal"; >> + }; >> + >> + clk32k: clock-controller@e001d500 { >> + compatible = "microchip,sama7d65-sckc", "microchip,sam9x60-sckc"; >> + reg = <0xe001d500 0x4>; >> + clocks = <&slow_xtal>; >> + #clock-cells = <1>; >> + }; >> + >> + sdmmc1: mmc@e1208000 { >> + compatible = "microchip,sama7d65-sdhci", "microchip,sam9x60-sdhci"; >> + reg = <0xe1208000 0x400>; >> + interrupts = ; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 76>, <&pmc PMC_TYPE_GCK 76>; >> + clock-names = "hclock", "multclk"; >> + assigned-clocks = <&pmc PMC_TYPE_GCK 76>; >> + assigned-clock-rates = <200000000>; >> + assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_MCK1>; >> + status = "disabled"; >> + }; >> + >> + pit64b0: timer@e1800000 { >> + compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; >> + reg = <0xe1800000 0x100>; >> + interrupts = ; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 66>, <&pmc PMC_TYPE_GCK 66>; >> + clock-names = "pclk", "gclk"; >> + }; >> + >> + pit64b1: timer@e1804000 { >> + compatible = "microchip,sama7d65-pit64b", "microchip,sam9x60-pit64b"; >> + reg = <0xe1804000 0x100>; >> + interrupts = ; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 67>, <&pmc PMC_TYPE_GCK 67>; >> + clock-names = "pclk", "gclk"; >> + }; >> + >> + flx6: flexcom@e2020000 { >> + compatible = "microchip,sama7d65-flexcom", "atmel,sama5d2-flexcom"; >> + reg = <0xe2020000 0x200>; >> + ranges = <0x0 0xe2020000 0x800>; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; >> + status = "disabled"; >> + >> + uart6: serial@200 { >> + compatible = "microchip,sama7d65-usart", "atmel,at91sam9260-usart"; >> + reg = <0x200 0x200>; >> + atmel,usart-mode = ; > > Vendor specific props would be at the end, before states, according to [1]. > I'll adjust it while applying. > > [1] This is the link, sorry: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/dts-coding-style.rst#n122 Other than that: Reviewed-by: Claudiu Beznea