Re: [PATCH 2/4] irqchip: Add support for Amlogic A4 and A5 SoCs

[Xianwei Zhao <xianwei.zhao@amlogic.com>]

Hi Thomas,
    Thank you for your advice.

On 2025/2/21 17:07, Thomas Gleixner wrote:
> [You don't often get email from tglx@linutronix.de. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]
> 
> [ EXTERNAL EMAIL ]
> 
> On Wed, Feb 19 2025 at 15:29, Xianwei Zhao via wrote:
>>
>> +static int meson_ao_gpio_irq_set_type(struct meson_gpio_irq_controller *ctl,
>> +                                   unsigned int type, u32 *channel_hwirq)
>> +{
>> +     u32 val = 0;
>> +     unsigned int idx;
>> +
>> +     idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
>> +
>> +     type &= IRQ_TYPE_SENSE_MASK;
>> +
>> +     meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO, BIT(idx), 0);
>> +
>> +     if (type == IRQ_TYPE_EDGE_BOTH) {
>> +             val |= BIT(ctl->params->edge_both_offset + (idx));
>> +             meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_AO,
>> +                                        BIT(ctl->params->edge_both_offset + (idx)), val);
>> +             return 0;
>> +     }
>> +
>> +     if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
>> +             val |= BIT(ctl->params->pol_low_offset + idx);
>> +
>> +     if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
>> +             val |= BIT(ctl->params->edge_single_offset + idx);
>> +
>> +     meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
>> +                                BIT(idx) | BIT(12 + idx), val);
>> +
>> +     return 0;
>> +};
> 
> This function is a full copy of meson_s4_gpio_irq_set_type() with the
> only difference of:
> 
>             s/REG_EDGE_POL_S4/REG_EDGE_POL_AO/
> 
> Can you please stick that register offset into the parameter structure
> and use the function for both variants?
> 
> Thanks,
> 

Will do.

>          tglx