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Thu, 08 Oct 2026 22:36:03 -0700 (PDT) X-Received: by 2002:a05:7300:1343:b0:351:727d:b9c2 with SMTP id 5a478bee46e88-3537e05bd1bmr1914418eec.17.1791524162729; Thu, 08 Oct 2026 22:36:02 -0700 (PDT) Received: from [10.217.218.111] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3537ca76e5asm3674061eec.15.2026.10.08.22.35.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 08 Oct 2026 22:36:02 -0700 (PDT) Message-ID: <9fc86230-772c-44db-92bd-8ed842969c16@oss.qualcomm.com> Date: Fri, 9 Oct 2026 11:05:57 +0530 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 1/3] dmaengine: qcom: gpi: Add I2C bus recovery opcode support To: Mukesh Savaliya , Vinod Koul , Frank Li , Viken Dadhaniya , Andi Shyti Cc: linux-arm-msm@vger.kernel.org, dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-i2c@vger.kernel.org References: <20260826-i2c_bus_recovery-v1-0-203f0ec76f84@oss.qualcomm.com> <20260826-i2c_bus_recovery-v1-1-203f0ec76f84@oss.qualcomm.com> Content-Language: en-US From: Aniket RANDIVE In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Authority-Analysis: v=2.4 cv=E+1YNqdl c=1 sm=1 tr=0 ts=6ac87d44 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=EUspDBNiAAAA:8 a=S-CjDK4xD3VWIf0aO8QA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: 1wNphMhw2jbyNIL800GmXaejWr1NGJT2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA5MDAyMiBTYWx0ZWRfX69HV8S9DSN9S RBG0RGFgtTE9YqYcS0hVn+WVXLx8K5XMy0++0Cm2+pjYJCJKw1F7l5+fxCrfEhSA2C2xSI443l6 BGGiSp5KRTod3c4c9pRL3csvBjLVo4Y4y6ysvGtVuTbBATzgPvo8qMGPIMg9SIgfSLFEURAYlZV AlDzQNseCfGZn2775Yo8/H7yF3dShyHEAc9l5+zrvGM5GzGgfO906qVU7BBV/9YzMXP5Kpr7mRq guyfEItjw/N8MpMekR7JNPglTGZm1Hbeu66qmwWauvQd0av/PayxE+mW+FyU1cDrKL82eQ8zP9P ZTpmWvovmz75cNXS+wNALMVOCQGIE+9IftLP8IYtCiu9hM+JcvhgkPIeiuwg20nCflu1INahhsE OaTvXjVr3wzlIuBu51NJKLtK5y9BeHKoA++a9XZ2yGLJSMEwXPO3ZPHO6u/avOAWSdS2zujudM1 1Nz/87fj5PCdLt55L0w== X-Proofpoint-ORIG-GUID: 1wNphMhw2jbyNIL800GmXaejWr1NGJT2 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA5MDAyMiBTYWx0ZWRfXztjNxscVgXHm 0j+oeupDeNeuL6n6EhMszMnArJ62wK4eAMMxPE0nlO8YFrU+TBzvS1W2HJRtHADrMUrpvF1CTDz odtOl1F24o7itZ9LoErDhBZRkrvp6D8= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-09_02,2026-10-08_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 spamscore=0 phishscore=0 bulkscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610020000 definitions=main-2610090022 On 9/7/2026 10:44 AM, Mukesh Savaliya wrote: > > > On 8/26/2026 3:21 PM, Aniket Randive wrote: >> The I2C_BUS_CLEAR and I2C_STOP_ON_BUS GENI sequencer opcodes release a >> stuck I2C bus, but the GPI DMA driver has no way to emit these >> zero-payload control commands, so an I2C controller using GPI DMA >> cannot recover the bus. >> >> Add I2C_BUS_CLEAR and I2C_STOP_ON_BUS to enum i2c_op so I2C drivers can >> request them through gpi_i2c_config.op. Handle them in >> gpi_create_i2c_tre() by emitting a CONFIG TRE (when set_config is set) >> followed by a GO TRE with IEOT set and no DMA TRE, and reserve the >> matching number of ring entries in gpi_prep_slave_sg(). >> > > start with problem statement which is being fixed by the respective patch. > > Rest of the message can be simplified as below - more you can add. > > Allow GPI DMA clients to issue the GENI I2C_BUS_CLEAR and > I2C_STOP_ON_BUS commands used for I2C bus recovery. > > Add the new opcodes to the GPI I2C interface and generate the > corresponding CONFIG/GO TRE sequence without data DMA transfers. > Adjust TRE reservation logic to account for these commands. > I will update the commit message. >> Signed-off-by: Aniket Randive >> --- >>   drivers/dma/qcom/gpi.c           | 30 ++++++++++++++++++++++++++++++ >>   include/linux/dma/qcom-gpi-dma.h |  2 ++ >>   2 files changed, 32 insertions(+) >> >> diff --git a/drivers/dma/qcom/gpi.c b/drivers/dma/qcom/gpi.c > > [...] > >> @@ -1825,6 +1843,18 @@ gpi_prep_slave_sg(struct dma_chan *chan, struct >> scatterlist *sgl, >>           nr_tre = 2; >>       if (direction == DMA_DEV_TO_MEM) /* rx */ >>           nr_tre = 1; >> +    /* >> +     * Recovery opcodes do not require DMA data TREs, only CONFIG >> +     * (for set_config) and GO TREs. Since gpi_prep_slave_sg() is >> +     * shared with SPI, verify the channel is I2C before accessing > Not only SPI, its for all GENI protocols. Can say common function for > all protocols. > sure. I will make it generic instead of single protocol. > May be once such conditions are rising, we need to think of better way > in design to handle such cases. >> +     * the configuration data. >> +     */ >> +    if (gchan->protocol == QCOM_GPI_I2C) { >> +        struct gpi_i2c_config *i2c = gchan->config; >> + >> +        if (i2c->op == I2C_BUS_CLEAR || i2c->op == I2C_STOP_ON_BUS) >> +            nr_tre = set_config ? 2 : 1; >> +    } > > [...] >