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X-CSE-ConnectionGUID: A0DOU9iXQMmfrMBMB4SC+g== X-CSE-MsgGUID: cfJcbzZVSKa7XsODuRwO9w== X-IronPort-AV: E=McAfee;i="6800,10657,11813"; a="81931227" X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="81931227" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa113.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 10:55:10 -0700 X-CSE-ConnectionGUID: Z3EvVDVNRSaJmgg8XNl1rg== X-CSE-MsgGUID: 3ISxqkw6TvCTTuxd6yYqdQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.24,199,1774335600"; d="scan'208";a="250844127" Received: from ijarvine-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.157]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2026 10:55:05 -0700 From: =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= Date: Thu, 11 Jun 2026 20:55:01 +0300 (EEST) To: Hans Zhang <18255117159@163.com> cc: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, kwilczynski@kernel.org, mani@kernel.org, jingoohan1@gmail.com, robh@kernel.org, linux-pci@vger.kernel.org, LKML , Shawn Lin Subject: Re: [PATCH v7 3/3] PCI: dwc: Use common speed conversion function In-Reply-To: <20260407130450.1489318-4-18255117159@163.com> Message-ID: <9fed4498-0218-872c-0fb2-92c33c8726b7@linux.intel.com> References: <20260407130450.1489318-1-18255117159@163.com> <20260407130450.1489318-4-18255117159@163.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII On Tue, 7 Apr 2026, Hans Zhang wrote: > Replace the private switch-based speed conversion in > dw_pcie_link_set_max_speed() with the public pci_bus_speed2lnkctl2() > function. > > This eliminates duplicate conversion logic and ensures consistency with > other PCIe drivers, while handling invalid speeds by falling back to > hardware capabilities. > > Signed-off-by: Hans Zhang <18255117159@163.com> > Reviewed-by: Shawn Lin > Acked-by: Manivannan Sadhasivam > --- > drivers/pci/controller/dwc/pcie-designware.c | 28 +++++++------------- > 1 file changed, 9 insertions(+), 19 deletions(-) > > diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c > index 06792ba92aa7..10895f6a8e6e 100644 > --- a/drivers/pci/controller/dwc/pcie-designware.c > +++ b/drivers/pci/controller/dwc/pcie-designware.c > @@ -843,8 +843,10 @@ EXPORT_SYMBOL_GPL(dw_pcie_upconfig_setup); > > static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) > { > - u32 cap, ctrl2, link_speed; > + u32 cap, ctrl2; > + enum pci_bus_speed link_speed; > u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); > + u16 ctrl2_speed; > > cap = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); > > @@ -861,30 +863,18 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci) > ctrl2 = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCTL2); > ctrl2 &= ~PCI_EXP_LNKCTL2_TLS; Not directly related to this patch but I wonder why this function gets the speed from LNKCTL2 instead of taking it from LNKCAP2_SLS. > > - switch (pcie_get_link_speed(pci->max_link_speed)) { > - case PCIE_SPEED_2_5GT: > - link_speed = PCI_EXP_LNKCTL2_TLS_2_5GT; > - break; > - case PCIE_SPEED_5_0GT: > - link_speed = PCI_EXP_LNKCTL2_TLS_5_0GT; > - break; > - case PCIE_SPEED_8_0GT: > - link_speed = PCI_EXP_LNKCTL2_TLS_8_0GT; > - break; > - case PCIE_SPEED_16_0GT: > - link_speed = PCI_EXP_LNKCTL2_TLS_16_0GT; > - break; > - default: > + link_speed = pcie_get_link_speed(pci->max_link_speed); > + ctrl2_speed = pci_bus_speed2lnkctl2(link_speed); > + if (ctrl2_speed == 0) { > /* Use hardware capability */ > - link_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); > + ctrl2_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, cap); > ctrl2 &= ~PCI_EXP_LNKCTL2_HASD; > - break; > } I again lament a bit that pcie_capability_read_*() cannot be used early in the controller drivers, which might allow using e.g. pcie_get_supported_speeds() here (depending on whether the small differences this function has compared it are really meaningful or not). But this is not really a problem this series is trying to address so as stated in my comment to the other patch, no objection to this change. > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | link_speed); > + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCTL2, ctrl2 | ctrl2_speed); > > cap &= ~((u32)PCI_EXP_LNKCAP_SLS); > - dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | link_speed); > + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, cap | ctrl2_speed); > > } > > -- i.