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Fri, 23 May 2025 12:30:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFd+qzCAswhS3iuiKWeZE50Wf+7n1+LX7vli2jZxIWG36wkuD8DiM8xlaNuqX/4ezVASlQWyA== X-Received: by 2002:a05:6214:1d23:b0:6e6:6964:ca77 with SMTP id 6a1803df08f44-6fa9d29c58dmr11207166d6.28.1748028658328; Fri, 23 May 2025 12:30:58 -0700 (PDT) Received: from [192.168.40.164] ([70.105.235.240]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6f8b08ac5ddsm118552726d6.44.2025.05.23.12.30.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 23 May 2025 12:30:57 -0700 (PDT) Message-ID: <9ffc7686-0dc0-4978-8cd8-f12a1c148b63@redhat.com> Date: Fri, 23 May 2025 15:30:52 -0400 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 2/5] KVM: arm64: New function to determine hardware cache management support Content-Language: en-US To: ankita@nvidia.com, jgg@nvidia.com, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, ryan.roberts@arm.com, shahuang@redhat.com, lpieralisi@kernel.org, david@redhat.com Cc: aniketa@nvidia.com, cjia@nvidia.com, kwankhede@nvidia.com, kjaju@nvidia.com, targupta@nvidia.com, vsethi@nvidia.com, acurrid@nvidia.com, apopple@nvidia.com, jhubbard@nvidia.com, danw@nvidia.com, zhiw@nvidia.com, mochs@nvidia.com, udhoke@nvidia.com, dnigam@nvidia.com, alex.williamson@redhat.com, sebastianene@google.com, coltonlewis@google.com, kevin.tian@intel.com, yi.l.liu@intel.com, ardb@kernel.org, akpm@linux-foundation.org, gshan@redhat.com, linux-mm@kvack.org, tabba@google.com, qperret@google.com, seanjc@google.com, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, maobibo@loongson.cn References: <20250523154445.3779-1-ankita@nvidia.com> <20250523154445.3779-3-ankita@nvidia.com> From: Donald Dutile In-Reply-To: <20250523154445.3779-3-ankita@nvidia.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 5/23/25 11:44 AM, ankita@nvidia.com wrote: > From: Ankit Agrawal > > The hardware supports safely mapping PFNMAP as cacheable if it > is capable of managing cache. This can be determined by the presence > of FWB (Force Write Back) and CACHE_DIC feature. > > When FWB is not enabled, the kernel expects to trivially do cache > management by flushing the memory by linearly converting a kvm_pte to > phys_addr to a KVA. The cache management thus relies on memory being > mapped. Since the GPU device memory is not kernel mapped, exit when > the FWB is not supported. Similarly, ARM64_HAS_CACHE_DIC allows KVM > to avoid flushing the icache and turns icache_inval_pou() into a NOP. > So the cacheable PFNMAP is contingent on these two hardware features. > > Introduce a new function to make the check for presence of those > features. > > CC: David Hildenbrand > Signed-off-by: Ankit Agrawal > --- > arch/arm64/kvm/mmu.c | 12 ++++++++++++ > include/linux/kvm_host.h | 2 ++ > 2 files changed, 14 insertions(+) > > diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c > index 305a0e054f81..124655da02ca 100644 > --- a/arch/arm64/kvm/mmu.c > +++ b/arch/arm64/kvm/mmu.c > @@ -1287,6 +1287,18 @@ void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, > kvm_nested_s2_wp(kvm); > } > > +/** > + * kvm_arch_supports_cacheable_pfnmap() - Determine whether hardware > + * supports cache management. > + * > + * Return: True if FWB and DIC is supported. > + */ > +bool kvm_arch_supports_cacheable_pfnmap(void) > +{ > + return cpus_have_final_cap(ARM64_HAS_STAGE2_FWB) && > + cpus_have_final_cap(ARM64_HAS_CACHE_DIC); > +} > + > static void kvm_send_hwpoison_signal(unsigned long address, short lsb) > { > send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, lsb, current); > diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h > index 291d49b9bf05..3750d216d456 100644 > --- a/include/linux/kvm_host.h > +++ b/include/linux/kvm_host.h > @@ -1231,6 +1231,8 @@ void kvm_arch_flush_shadow_all(struct kvm *kvm); > /* flush memory translations pointing to 'slot' */ > void kvm_arch_flush_shadow_memslot(struct kvm *kvm, > struct kvm_memory_slot *slot); > +/* hardware support cache management */ > +bool kvm_arch_supports_cacheable_pfnmap(void); > Won't this cause a build warning on non-ARM builds, b/c there is no resolution of this function for the other arch's? Need #ifdef or default-rtn-0 function for arch's that don't have this function? > int kvm_prefetch_pages(struct kvm_memory_slot *slot, gfn_t gfn, > struct page **pages, int nr_pages);