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The Tegra114 speedo > code computes this value but never stores it, so the DFLL uses speedo > 0 and only the c0 coefficient remains. For CPU speedo IDs 1 to 3 c0 is > 2190643 to 3395401, so "mv * 1000" in round_cvb_voltage() overflows and > the OPP voltages are wrong. >=20 > This is currently hidden by a zero voltage step with Palmas regulators, > fixed in the next patch. With both fixes the CPU OPPs range from 1000 mV > to 1270 mV on a device with CPU speedo 1742, which matches the vendor > kernel. >=20 > Store the SoC speedo value as well, as Tegra124 and Tegra210 do. >=20 > Fixes: 5aba939e80f4 ("clk: tegra: dfll: Add CVB tables for Tegra114") > Cc: stable@vger.kernel.org > Signed-off-by: Patrick Fischer > --- > drivers/soc/tegra/fuse/speedo-tegra114.c | 3 +++ > 1 file changed, 3 insertions(+) >=20 > diff --git a/drivers/soc/tegra/fuse/speedo-tegra114.c b/drivers/soc/tegra= /fuse/speedo-tegra114.c > index 1e6c2b5be759..8bf1a1b1287a 100644 > --- a/drivers/soc/tegra/fuse/speedo-tegra114.c > +++ b/drivers/soc/tegra/fuse/speedo-tegra114.c > @@ -92,6 +92,9 @@ void __init tegra114_init_speedo_data(struct tegra_sku_= info *sku_info) > cpu_speedo_val =3D tegra_fuse_read_early(FUSE_CPU_SPEEDO_1) + 1024; > soc_speedo_val =3D tegra_fuse_read_early(FUSE_SOC_SPEEDO_0); > =20 > + sku_info->cpu_speedo_value =3D cpu_speedo_val; > + sku_info->soc_speedo_value =3D soc_speedo_val; > + > for (i =3D 0; i < CPU_PROCESS_CORNERS; i++) > if (cpu_speedo_val < cpu_process_speedos[threshold][i]) > break; >=20 > --=20 > 2.56.0 >=20 >=20 >=20 Reviewed-by: Mikko Perttunen Tested-by: Mikko Perttunen # Dalmore