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Mon, 20 Apr 2026 06:44:17 +0000 Received: from AM0PR04MB5220.eurprd04.prod.outlook.com ([fe80::cbbc:93fd:f7b0:76e5]) by AM0PR04MB5220.eurprd04.prod.outlook.com ([fe80::cbbc:93fd:f7b0:76e5%4]) with mapi id 15.20.9818.032; Mon, 20 Apr 2026 06:44:16 +0000 From: Hongxing Zhu To: Peng Fan , "abelvesa@kernel.org" , "mturquette@baylibre.com" , "sboyd@kernel.org" , Frank Li , "s.hauer@pengutronix.de" , "festevam@gmail.com" CC: "linux-clk@vger.kernel.org" , "imx@nxp.com" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "kernel@pengutronix.de" Subject: RE: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95 Thread-Topic: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95 Thread-Index: AQHczkP/2tDj/rWRvEKEo2F74GRsJLXi+qSAgASIknA= Date: Mon, 20 Apr 2026 06:44:16 +0000 Message-ID: References: <20260417082910.489995-1-hongxing.zhu@nxp.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nxp.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: AM0PR04MB5220.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 22b36902-4536-429d-d6e8-08de9ea83e08 X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Apr 2026 06:44:16.5346 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: g8aE6chUAza+5VFcXym+Fce4sTZ8p7TT+0qlRcC/g9bsMMUlp/tK2qDSDfOl2MLwOVt7WyE4pV8fUIaWN8eQOA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DBBPR04MB7737 > -----Original Message----- > From: Peng Fan > Sent: Friday, April 17, 2026 5:22 PM > To: Hongxing Zhu ; abelvesa@kernel.org; > mturquette@baylibre.com; sboyd@kernel.org; Frank Li ; > s.hauer@pengutronix.de; festevam@gmail.com > Cc: linux-clk@vger.kernel.org; imx@nxp.com; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; kernel@pengutro= nix.de > Subject: RE: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch= on > i.MX95 >=20 > Hi Richard, >=20 > > Subject: [PATCH v1] clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch > > on > > i.MX95 > > > > When the internal PLL is used as the PCIe reference clock source on > > i.MX95, a REFCLK rise-fall time mismatch is observed during PCIe Gen1 > > compliance testing with the Lfast IO analyzer. > > > > Fix this issue by configuring the IREF_TX field to 0xF (15), which > > adjusts the transmitter current reference to meet the PCIe > > specification timing requirements. >=20 > BLK CTRL in HSIOMIX should be save/restore for the settings you configure= d in > probe phase. Hi Peng: The register containing the pre-configured settings is the same as the gate-clock register. Therefore, its value will be saved and restored during the suspend/resume procedures. Thanks. Best Regards Richard Zhu >=20 > Regards > Peng. >=20 > > > > Signed-off-by: Richard Zhu > > --- > > drivers/clk/imx/clk-imx95-blk-ctl.c | 7 +++++++ > > 1 file changed, 7 insertions(+) > > > > diff --git a/drivers/clk/imx/clk-imx95-blk-ctl.c > > b/drivers/clk/imx/clk- imx95-blk-ctl.c index > > 1f9259f45607..bc6957299cec 100644 > > --- a/drivers/clk/imx/clk-imx95-blk-ctl.c > > +++ b/drivers/clk/imx/clk-imx95-blk-ctl.c > > @@ -44,6 +44,8 @@ struct imx95_blk_ctl_clk_dev_data { > > const char * const *parent_names; > > u32 num_parents; > > u32 reg; > > + u32 reg_init_msk; > > + u32 reg_init_val; > > u32 bit_idx; > > u32 bit_width; > > u32 clk_type; > > @@ -289,6 +291,8 @@ static const struct imx95_blk_ctl_clk_dev_data > > hsio_blk_ctl_clk_dev_data[] =3D { > > .parent_names =3D (const char *[]){ "func_out_en", }, > > .num_parents =3D 1, > > .reg =3D 0, > > + .reg_init_msk =3D GENMASK(10, 7), > > + .reg_init_val =3D GENMASK(10, 7), > > .bit_idx =3D 6, > > .bit_width =3D 1, > > .type =3D CLK_GATE, > > @@ -410,6 +414,9 @@ static int imx95_bc_probe(struct platform_device > > *pdev) > > const struct imx95_blk_ctl_clk_dev_data *data =3D &bc- > > >pdata->clk_dev_data[i]; > > void __iomem *reg =3D base + data->reg; > > > > + if (data->reg_init_msk) > > + writel((readl(reg) & ~data->reg_init_msk) | > > data->reg_init_val, > > +reg); > > + > > if (data->type =3D=3D CLK_MUX) { > > hws[i] =3D clk_hw_register_mux(dev, data- > > >name, data->parent_names, > > data- > > >num_parents, data->flags, reg, > > -- > > 2.37.1