From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751878AbdHADdU (ORCPT ); Mon, 31 Jul 2017 23:33:20 -0400 Received: from mail-he1eur01on0079.outbound.protection.outlook.com ([104.47.0.79]:22889 "EHLO EUR01-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751759AbdHADdS (ORCPT ); Mon, 31 Jul 2017 23:33:18 -0400 From: "A.s. Dong" To: Daniel Lezcano , "linux-kernel@vger.kernel.org" CC: "linux-arm-kernel@lists.infradead.org" , "tglx@linutronix.de" , "shawnguo@kernel.org" , Jacky Bai , Anson Huang , "dongas86@gmail.com" , "kernel@pengutronix.de" , "Arnd Bergmann" Subject: RE: [PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support Thread-Topic: [PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support Thread-Index: AQHS9TeVqpgKpQlux0asTpEHtlfhwqJuKFOAgADY3CA= Date: Tue, 1 Aug 2017 03:33:15 +0000 Message-ID: References: <1499222112-9988-1-git-send-email-aisheng.dong@nxp.com> <1499222112-9988-3-git-send-email-aisheng.dong@nxp.com> In-Reply-To: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=aisheng.dong@nxp.com; x-originating-ip: [192.158.241.86] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;AM3PR04MB1315;7:euii2vYym0EITFxDYDM6OXmKXs58/z0zgfZokiCtRA/4mMiT9x2mAcSw1gMRwEGF8tXSnaPjfr8QFofgx+RE8G4U/BXm5l3PdYOjJMS6LGfErfuD3m3L3PGNceGMH7ZkqAL5Yyk6orNZeFE7NXg8s2g45BzwDQyLTAdCdytZCgs17GCc2rP7PSwK+mat/SjPTY4GWbtOl0eyQnktXirKrU07YPrpGrXFYRWRKb1BspXhqqsQ0cg/FC7r5rxd73mpQhOq74arafBcQyWwCLMY5Updq1nIeRkxuUsb2jDBGrxI4TNjQjEfv97mYTiNnYJroRdF+6zD3/1Tc/k3Pbmv5Y15LtSyWVJOvG58qrTRNqzWY1vNLZWN4d0nZzU+XHDLbI2wCNAlKZ5jlv/nrBgMwWPQH6x1D/5j8VrVhG/HEB9gv9l6F5fmDB0j9JQRrJQY2Up9iycsk9z7b9hrPx8spdZ4T1Jmx4aLhnjnp6du3fXLkEvXZyqukVaY/mRQvPLHwFdHSxFlWlOby44pnULzD9ZMXIn26KXfh5iQpNMtoSe4knqO0BxTfBPOszNIxow+vu7Uet6+GWm8Oi3eQp7U4WN6XRIT9mEbWyQGtvGXz3xKX6k3tilptWiDPR5wsA9Z0NAHoabSzOTbYZzEvK3tcJjccHHQGUtGqKq+xUVrvoVFNgHV1rhPP++UNFiOrVDpfab4+eS3t2DSYx++EqWTPVarO7s/LeFPv+njPWDJGeuKy8zZbet9nXiBU1KzfPT24cpJf2BThIQJGqplgbIV93TV7BXBUgDlnahXFXuegQg= x-forefront-antispam-report: SFV:SKI;SCL:-1;SFV:NSPM;SFS:(10009020)(6009001)(39860400002)(39400400002)(39850400002)(39840400002)(39450400003)(39410400002)(24454002)(13464003)(377454003)(54534003)(199003)(189002)(5660300001)(14454004)(7696004)(7736002)(105586002)(305945005)(4326008)(101416001)(2906002)(33656002)(2950100002)(106356001)(1720100001)(53546010)(97736004)(6306002)(25786009)(9686003)(54906002)(68736007)(53936002)(478600001)(6436002)(189998001)(54356999)(99286003)(55016002)(2900100001)(38730400002)(53376002)(8676002)(6246003)(8936002)(74316002)(81166006)(81156014)(39060400002)(102836003)(6116002)(50986999)(66066001)(76176999)(3280700002)(3846002)(6506006)(3660700001)(86362001)(229853002)(2501003)(5250100002);DIR:OUT;SFP:1101;SCL:1;SRVR:AM3PR04MB1315;H:AM3PR04MB306.eurprd04.prod.outlook.com;FPR:;SPF:None;PTR:InfoNoRecords;A:1;MX:1;LANG:en; x-ms-office365-filtering-correlation-id: 876911eb-8ed1-4604-4fa4-08d4d88e0b8b x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(300000500095)(300135000095)(300000501095)(300135300095)(22001)(300000502095)(300135100095)(2017030254152)(48565401081)(300000503095)(300135400095)(2017052603031)(201703131423075)(201703031133081)(201702281549075)(300000504095)(300135200095)(300000505095)(300135600095)(300000506095)(300135500095);SRVR:AM3PR04MB1315; x-ms-traffictypediagnostic: AM3PR04MB1315: x-exchange-antispam-report-test: UriScan:(148322886591682)(31418570063057)(9452136761055)(185117386973197)(258649278758335)(86561027422486)(81227570615382)(64217206974132); x-microsoft-antispam-prvs: x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(601004)(2401047)(5005006)(8121501046)(3002001)(93006095)(93001095)(10201501046)(100000703101)(100105400095)(6055026)(6041248)(20161123558100)(20161123560025)(20161123555025)(20161123562025)(20161123564025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(6072148)(100000704101)(100105200095)(100000705101)(100105500095);SRVR:AM3PR04MB1315;BCL:0;PCL:0;RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);SRVR:AM3PR04MB1315; x-forefront-prvs: 0386B406AA spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Aug 2017 03:33:15.5154 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR04MB1315 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id v713XQB1025947 Hi Daniel, > -----Original Message----- > From: Daniel Lezcano [mailto:daniel.lezcano@linaro.org] > Sent: Monday, July 31, 2017 10:29 PM > To: A.s. Dong; linux-kernel@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org; tglx@linutronix.de; > shawnguo@kernel.org; Jacky Bai; Anson Huang; dongas86@gmail.com; > kernel@pengutronix.de; Arnd Bergmann > Subject: Re: [PATCH V4 2/2] timer: imx-tpm: add imx tpm timer support > > On 05/07/2017 04:35, Dong Aisheng wrote: > > IMX Timer/PWM Module (TPM) supports both timer and pwm function while > > this patch only adds the timer support. PWM would be added later. > > > > The TPM counter, compare and capture registers are clocked by an > > asynchronous clock that can remain enabled in low power modes. > > > > NOTE: We observed in a very small probability, the bus fabric > > contention between GPU and A7 may results a few cycles delay of > > writing CNT registers which may cause the min_delta event got missed, > > so we need add a ETIME check here in case it happened. > > > > Cc: Daniel Lezcano > > Cc: Arnd Bergmann > > Cc: Thomas Gleixner > > Cc: Shawn Guo > > Cc: Anson Huang > > Cc: Bai Ping > > Signed-off-by: Dong Aisheng > > > > --- > > ChangeLog: > > v3->v4: > > * also add ETIME explanation in function > > v2->v3: > > * address all comments from Daniel Lezcano > > * add more explaination on ETIME check in commit message > > v1->v2: > > * change to readl/writel from __raw_readl/writel according to Arnd's > > suggestion to avoid endian issue > > * add help information in Kconfig > > * add more error checking > > --- > > drivers/clocksource/Kconfig | 8 ++ > > drivers/clocksource/Makefile | 1 + > > drivers/clocksource/timer-imx-tpm.c | 239 > > ++++++++++++++++++++++++++++++++++++ > > 3 files changed, 248 insertions(+) > > create mode 100644 drivers/clocksource/timer-imx-tpm.c > > [ ... ] > > > +static struct irqaction tpm_timer_irq = { > > + .name = "i.MX7ULP TPM Timer", > > + .flags = IRQF_TIMER | IRQF_IRQPOLL, > > + .handler = tpm_timer_interrupt, > > + .dev_id = &clockevent_tpm, > > +}; > > > > Please remove the structure above and use request_irq instead of setup_irq > below + return code checking. > Okay, will switch to it. > > +static int __init tpm_clockevent_init(unsigned long rate, int irq) { > > + setup_irq(irq, &tpm_timer_irq); > > + > > + clockevent_tpm.cpumask = cpumask_of(0); > > + clockevent_tpm.irq = irq; > > + clockevents_config_and_register(&clockevent_tpm, > > + rate, 300, 0xfffffffe); > > + > > + return 0; > > +} > > + > > +static int __init tpm_timer_init(struct device_node *np) { > > [ ... ] > > > + rate = clk_get_rate(per) >> 3; > > Why ? > Because TPM internally is configured to divide 8. The full context is: /* increase per cnt, div 8 by default */ writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT, timer_base + TPM_SC); /* set MOD register to maximum for free running mode */ writel(0xffffffff, timer_base + TPM_MOD); rate = clk_get_rate(per) >> 3; > > + tpm_clocksource_init(rate); > > + tpm_clockevent_init(rate, irq); > > Check. > Currently non of them return error code, do I still need to check? > > + return 0; > > + > > +err_per_clk_enable: > > + clk_disable_unprepare(ipg); > > +err_ipg_clk_enable: > > No need to add an extra label. > Okay, will remove one. > > +err_clk_get: > > + clk_put(per); > > + clk_put(ipg); > > +err_iomap: > > + iounmap(timer_base); > > + return ret; > > +} > > +CLOCKSOURCE_OF_DECLARE(imx7ulp, "fsl,imx7ulp-tpm", tpm_timer_init); > > CLOCKSOURCE_OF_DECLARE is renamed to TIMER_OF_DECLARE. > Looks new, will change to it. Thanks! Regards Dong Aisheng > Thanks! > > -- Daniel > > > -- > Linaro.org │ Open source software for ARM SoCs > > Follow Linaro: Facebook | > Twitter | blog/> Blog