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Wed, 27 Nov 2019 16:33:13 +0000 Received: from AM5PR1001MB0994.EURPRD10.PROD.OUTLOOK.COM ([fe80::5525:87da:ca4:e8df]) by AM5PR1001MB0994.EURPRD10.PROD.OUTLOOK.COM ([fe80::5525:87da:ca4:e8df%7]) with mapi id 15.20.2474.023; Wed, 27 Nov 2019 16:33:12 +0000 From: Adam Thomson To: Mark Brown , Adam Thomson CC: Sebastian Reichel , Support Opensource , Liam Girdwood , Jaroslav Kysela , Takashi Iwai , "alsa-devel@alsa-project.org" , "linux-kernel@vger.kernel.org" , "kernel@collabora.com" Subject: RE: [PATCHv2 6/6] ASoC: da7213: Add default clock handling Thread-Topic: [PATCHv2 6/6] ASoC: da7213: Add default clock handling Thread-Index: AQHVn7aXMyQuMXvm70+jyJLut64noaeWIihwgAeSgICAAAQ4gIAACJ3wgAADHgCAARqUMIAAHxOAgAAPlwCAACS4AIAADJyg Date: Wed, 27 Nov 2019 16:33:12 +0000 Message-ID: References: <20191120152406.2744-1-sebastian.reichel@collabora.com> <20191120152406.2744-7-sebastian.reichel@collabora.com> <20191126170841.GC4205@sirena.org.uk> <20191126175040.GD4205@sirena.org.uk> <20191127123317.GA4879@sirena.org.uk> <20191127154030.GD4879@sirena.org.uk> In-Reply-To: <20191127154030.GD4879@sirena.org.uk> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [165.225.80.228] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4dc811cf-76c5-4f23-ea8a-08d773577f2f x-ms-traffictypediagnostic: AM5PR1001MB0979: x-ms-exchange-sharedmailbox-routingagent-processed: True x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8882; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: diasemi.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4dc811cf-76c5-4f23-ea8a-08d773577f2f X-MS-Exchange-CrossTenant-originalarrivaltime: 27 Nov 2019 16:33:12.7800 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 511e3c0e-ee96-486e-a2ec-e272ffa37b7c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: rStooYcqh+zMnODB5AeulISbXGOri4ODkFw0TuYcD9wOkb37ie32M+rtt8Vk9nc5ga0C0wyCH65XwLcJ0RYUMF/d3krjIGY3V47EpmTd5UU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR1001MB0979 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 27 November 2019 15:41, Mark Brown wrote: > On Wed, Nov 27, 2019 at 01:42:54PM +0000, Adam Thomson wrote: >=20 > > nicest solution here though. I guess we're stuck with people having to = manually > > configure the PLL for bypass when a non-generic machine driver inits, t= o avoid > > the initial double config, as I don't see other options unless you have > > something to specify at init that it's auto or manual, and this doesn't= feel > > like a DT device specific property thing as it's more software than har= dware. > > At least Sebastian's patch has a good comment block to highlight this. >=20 > Not sure I follow here - if we're configuring the PLL explicitly then > I'd expect the PLL to be configured first, then the SYSCLK, so I'd > expect that the automatic PLL configuration wouldn't kick in. The PLL in the codec relies on MCLK. The MCLK rate can be specified/configu= red by a machine driver using the relevant codec sysclk function, as is done in= a number of drivers. Surely that has to happen first before we configure the = PLL as the PLL functions needs to know what rate is coming in so the correct dividers can be applied for the required internal clocking to match up with= the desired sample rates. I guess I'm still missing something regarding your discussion around SYSCLK?