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andy.yan@rock-chips.com, cristian.ciocaltea@collabora.com, devicetree@vger.kernel.org, dmitry.baryshkov@oss.qualcomm.com, dri-devel@lists.freedesktop.org, heiko@sntech.de, hjc@rock-chips.com, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, mripard@kernel.org, naoki@radxa.com, neil.armstrong@linaro.org, robh@kernel.org, sebastian.reichel@collabora.com, stephen@radxa.com, yubing.zhang@rock-chips.com References: <20250822063959.692098-1-andyshrk@163.com> Subject: Re: [PATCH v7 00/10] Add support for RK3588 DisplayPort Controller Content-Language: en-US From: Maud Spierings In-Reply-To: <20250822063959.692098-1-andyshrk@163.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: AM0PR04CA0062.eurprd04.prod.outlook.com (2603:10a6:208:1::39) To AM7P189MB1009.EURP189.PROD.OUTLOOK.COM (2603:10a6:20b:175::17) X-Microsoft-Original-Message-ID: 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X-OriginatorOrg: sct-15-20-8534-20-msonline-outlook-2ef4d.templateTenant X-MS-Exchange-CrossTenant-Network-Message-Id: 5a6505f0-9eb4-44aa-ff6a-08dde70a2d74 X-MS-Exchange-CrossTenant-AuthSource: AM7P189MB1009.EURP189.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Aug 2025 14:41:45.9471 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7P189MB0709 Hello Andy, > There are two DW DPTX based DisplayPort Controller on rk3588 which > are compliant with the DisplayPort Specification Version 1.4 with > the following features: > > * DisplayPort 1.4a > * Main Link: 1/2/4 lanes > * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps > * AUX channel 1Mbps > * Single Stream Transport(SST) > * Multistream Transport (MST) > * Type-C support (alternate mode) > * HDCP 2.2, HDCP 1.3 > * Supports up to 8/10 bits per color component > * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0 > * Pixel clock up to 594MHz > * I2S, SPDIF audio interface > > The current version of this patch series only supports basic display outputs. > I conducted tests with DP0 in 1080p and 4K@60 YCbCr4:2:0 modes; the ALT/Type-C > mode was tested on Rock 5B Is there an example of this? I want to implement it for the usb-c port on the orangepi 5 plus, but I can't quite figure out where I would have to link the DP output endpoint to? The usb-c endpoints are all done. Is it to another endpoint in the usbdp_phy? The only endpoints there seem to be outputs. Or is it supposed to be left unconnected for the ALT/type-C mode? I've tried reading through all the relevant dt-bindings but can't find it. Kind regards, Maud